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https://github.com/yuzu-emu/unicorn.git
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exec.c: Make address_space_rw take transaction attributes
Make address_space_rw take transaction attributes, rather than always using the 'unspecified' attributes. Backports commit 5c9eb0286c819c1836220a32f2e1a7b5004ac79a from qemu
This commit is contained in:
parent
6143189cce
commit
b94c89e559
53
qemu/exec.c
53
qemu/exec.c
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@ -1254,13 +1254,16 @@ static MemTxResult subpage_read(struct uc_struct* uc, void *opaque, hwaddr addr,
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{
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{
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subpage_t *subpage = opaque;
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subpage_t *subpage = opaque;
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uint8_t buf[4];
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uint8_t buf[4];
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MemTxResult res;
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#if defined(DEBUG_SUBPAGE)
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#if defined(DEBUG_SUBPAGE)
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printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__,
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printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__,
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subpage, len, addr);
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subpage, len, addr);
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#endif
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#endif
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if (address_space_read(subpage->as, addr + subpage->base, buf, len)) {
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res = address_space_read(subpage->as, addr + subpage->base,
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return MEMTX_DECODE_ERROR;
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attrs, buf, len);
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if (res) {
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return res;
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}
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}
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switch (len) {
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switch (len) {
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case 1:
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case 1:
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@ -1307,10 +1310,8 @@ static MemTxResult subpage_write(struct uc_struct* uc, void *opaque, hwaddr addr
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default:
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default:
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abort();
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abort();
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}
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}
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if (address_space_write(subpage->as, addr + subpage->base, buf, len)) {
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return address_space_write(subpage->as, addr + subpage->base,
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return MEMTX_DECODE_ERROR;
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attrs, buf, len);
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}
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return MEMTX_OK;
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}
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}
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static bool subpage_accepts(void *opaque, hwaddr addr,
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static bool subpage_accepts(void *opaque, hwaddr addr,
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@ -1649,8 +1650,8 @@ static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr)
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return l;
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return l;
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}
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}
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bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
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MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
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int len, bool is_write)
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uint8_t *buf, int len, bool is_write)
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{
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{
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hwaddr l;
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hwaddr l;
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uint8_t *ptr;
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uint8_t *ptr;
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@ -1658,7 +1659,6 @@ bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
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hwaddr addr1;
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hwaddr addr1;
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MemoryRegion *mr;
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MemoryRegion *mr;
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MemTxResult result = MEMTX_OK;
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MemTxResult result = MEMTX_OK;
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MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
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while (len > 0) {
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while (len > 0) {
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l = len;
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l = len;
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@ -1760,22 +1760,24 @@ bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
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return result;
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return result;
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}
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}
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bool address_space_write(AddressSpace *as, hwaddr addr,
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MemTxResult address_space_write(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
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const uint8_t *buf, int len)
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const uint8_t *buf, int len)
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{
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{
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return address_space_rw(as, addr, (uint8_t *)buf, len, true);
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return address_space_rw(as, addr, attrs, (uint8_t *)buf, len, true);
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}
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}
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bool address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len)
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MemTxResult address_space_read(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
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uint8_t *buf, int len)
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{
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{
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return address_space_rw(as, addr, buf, len, false);
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return address_space_rw(as, addr, attrs, buf, len, false);
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}
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}
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bool cpu_physical_memory_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
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bool cpu_physical_memory_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
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int len, int is_write)
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int len, int is_write)
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{
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{
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return address_space_rw(as, addr, buf, len, is_write);
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return address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED,
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buf, len, is_write) == MEMTX_OK;
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}
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}
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enum write_rom_type {
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enum write_rom_type {
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@ -1901,7 +1903,8 @@ void *address_space_map(AddressSpace *as,
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memory_region_ref(mr);
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memory_region_ref(mr);
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as->uc->bounce.mr = mr;
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as->uc->bounce.mr = mr;
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if (!is_write) {
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if (!is_write) {
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address_space_read(as, addr, as->uc->bounce.buffer, l);
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address_space_read(as, addr, MEMTXATTRS_UNSPECIFIED,
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as->uc->bounce.buffer, l);
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}
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}
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*plen = l;
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*plen = l;
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@ -1951,7 +1954,8 @@ void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
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return;
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return;
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}
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}
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if (is_write) {
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if (is_write) {
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address_space_write(as, as->uc->bounce.addr, as->uc->bounce.buffer, access_len);
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address_space_write(as, as->uc->bounce.addr, MEMTXATTRS_UNSPECIFIED,
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as->uc->bounce.buffer, access_len);
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}
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}
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qemu_vfree(as->uc->bounce.buffer);
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qemu_vfree(as->uc->bounce.buffer);
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as->uc->bounce.buffer = NULL;
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as->uc->bounce.buffer = NULL;
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@ -2094,7 +2098,7 @@ uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr)
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uint32_t ldub_phys(AddressSpace *as, hwaddr addr)
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uint32_t ldub_phys(AddressSpace *as, hwaddr addr)
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{
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{
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uint8_t val;
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uint8_t val;
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address_space_rw(as, addr, &val, 1, 0);
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address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, &val, 1, 0);
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return val;
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return val;
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}
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}
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@ -2242,7 +2246,7 @@ void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val)
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void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val)
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void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val)
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{
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{
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uint8_t v = val;
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uint8_t v = val;
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address_space_rw(as, addr, &v, 1, 1);
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address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, &v, 1, 1);
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}
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}
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/* warning: addr must be aligned */
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/* warning: addr must be aligned */
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@ -2306,19 +2310,19 @@ void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val)
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void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val)
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void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val)
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{
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{
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val = tswap64(val);
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val = tswap64(val);
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address_space_rw(as, addr, (void *) &val, 8, 1);
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address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, (void *) &val, 8, 1);
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}
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}
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void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val)
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void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val)
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{
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{
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val = cpu_to_le64(val);
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val = cpu_to_le64(val);
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address_space_rw(as, addr, (void *) &val, 8, 1);
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address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, (void *) &val, 8, 1);
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}
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}
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void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val)
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void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val)
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{
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{
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val = cpu_to_be64(val);
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val = cpu_to_be64(val);
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address_space_rw(as, addr, (void *) &val, 8, 1);
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address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, (void *) &val, 8, 1);
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}
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}
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/* virtual memory access for debug (includes writing to ROM) */
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/* virtual memory access for debug (includes writing to ROM) */
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@ -2342,7 +2346,8 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
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if (is_write) {
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if (is_write) {
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cpu_physical_memory_write_rom(cpu->as, phys_addr, buf, l);
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cpu_physical_memory_write_rom(cpu->as, phys_addr, buf, l);
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} else {
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} else {
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address_space_rw(cpu->as, phys_addr, buf, l, 0);
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address_space_rw(cpu->as, phys_addr, MEMTXATTRS_UNSPECIFIED,
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buf, l, 0);
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}
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}
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len -= l;
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len -= l;
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buf += l;
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buf += l;
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@ -807,41 +807,50 @@ void address_space_destroy(AddressSpace *as);
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/**
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/**
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* address_space_rw: read from or write to an address space.
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* address_space_rw: read from or write to an address space.
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*
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*
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* Return true if the operation hit any unassigned memory or encountered an
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* Return a MemTxResult indicating whether the operation succeeded
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* IOMMU fault.
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* or failed (eg unassigned memory, device rejected the transaction,
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* IOMMU fault).
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*
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*
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* @as: #AddressSpace to be accessed
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* @as: #AddressSpace to be accessed
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* @addr: address within that address space
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* @addr: address within that address space
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* @attrs: memory transaction attributes
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* @buf: buffer with the data transferred
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* @buf: buffer with the data transferred
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* @is_write: indicates the transfer direction
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* @is_write: indicates the transfer direction
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*/
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*/
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bool address_space_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
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MemTxResult address_space_rw(AddressSpace *as, hwaddr addr,
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int len, bool is_write);
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MemTxAttrs attrs, uint8_t *buf,
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int len, bool is_write);
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/**
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/**
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* address_space_write: write to address space.
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* address_space_write: write to address space.
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*
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*
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* Return true if the operation hit any unassigned memory or encountered an
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* Return a MemTxResult indicating whether the operation succeeded
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* IOMMU fault.
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* or failed (eg unassigned memory, device rejected the transaction,
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* IOMMU fault).
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*
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*
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* @as: #AddressSpace to be accessed
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* @as: #AddressSpace to be accessed
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* @addr: address within that address space
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* @addr: address within that address space
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* @attrs: memory transaction attributes
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* @buf: buffer with the data transferred
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* @buf: buffer with the data transferred
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*/
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*/
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bool address_space_write(AddressSpace *as, hwaddr addr,
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MemTxResult address_space_write(AddressSpace *as, hwaddr addr,
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const uint8_t *buf, int len);
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MemTxAttrs attrs,
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const uint8_t *buf, int len);
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/**
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/**
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* address_space_read: read from an address space.
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* address_space_read: read from an address space.
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*
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*
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* Return true if the operation hit any unassigned memory or encountered an
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* Return a MemTxResult indicating whether the operation succeeded
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* IOMMU fault.
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* or failed (eg unassigned memory, device rejected the transaction,
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* IOMMU fault).
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*
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*
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* @as: #AddressSpace to be accessed
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* @as: #AddressSpace to be accessed
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* @addr: address within that address space
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* @addr: address within that address space
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* @attrs: memory transaction attributes
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* @buf: buffer with the data transferred
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* @buf: buffer with the data transferred
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*/
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*/
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bool address_space_read(AddressSpace *as, hwaddr addr, uint8_t *buf, int len);
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MemTxResult address_space_read(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
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uint8_t *buf, int len);
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/* address_space_translate: translate an address range into an address space
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/* address_space_translate: translate an address range into an address space
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* into a MemoryRegion and an address range into that section
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* into a MemoryRegion and an address range into that section
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