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target-arm: Recognize ROR
Backports commit 8fb0ad8e16ab3d03433244a1a03e1df757342ad8 from qemu
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@ -3113,17 +3113,7 @@ static void disas_extract(DisasContext *s, uint32_t insn)
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tcg_rd = cpu_reg(s, rd);
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if (imm) {
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/* OPTME: we can special case rm==rn as a rotate */
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tcg_rm = read_cpu_reg(s, rm, sf);
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tcg_rn = read_cpu_reg(s, rn, sf);
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tcg_gen_shri_i64(tcg_ctx, tcg_rm, tcg_rm, imm);
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tcg_gen_shli_i64(tcg_ctx, tcg_rn, tcg_rn, bitsize - imm);
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tcg_gen_or_i64(tcg_ctx, tcg_rd, tcg_rm, tcg_rn);
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if (!sf) {
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tcg_gen_ext32u_i64(tcg_ctx, tcg_rd, tcg_rd);
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}
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} else {
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if (unlikely(imm == 0)) {
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/* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
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* so an extract from bit 0 is a special case.
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*/
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@ -3132,8 +3122,27 @@ static void disas_extract(DisasContext *s, uint32_t insn)
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} else {
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tcg_gen_ext32u_i64(tcg_ctx, tcg_rd, cpu_reg(s, rm));
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}
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} else if (rm == rn) { /* ROR */
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tcg_rm = cpu_reg(s, rm);
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if (sf) {
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tcg_gen_rotri_i64(tcg_ctx, tcg_rd, tcg_rm, imm);
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} else {
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TCGv_i32 tmp = tcg_temp_new_i32(tcg_ctx);
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tcg_gen_extrl_i64_i32(tcg_ctx, tmp, tcg_rm);
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tcg_gen_rotri_i32(tcg_ctx, tmp, tmp, imm);
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tcg_gen_extu_i32_i64(tcg_ctx, tcg_rd, tmp);
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tcg_temp_free_i32(tcg_ctx, tmp);
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}
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} else {
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tcg_rm = read_cpu_reg(s, rm, sf);
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tcg_rn = read_cpu_reg(s, rn, sf);
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tcg_gen_shri_i64(tcg_ctx, tcg_rm, tcg_rm, imm);
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tcg_gen_shli_i64(tcg_ctx, tcg_rn, tcg_rn, bitsize - imm);
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tcg_gen_or_i64(tcg_ctx, tcg_rd, tcg_rm, tcg_rn);
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if (!sf) {
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tcg_gen_ext32u_i64(tcg_ctx, tcg_rd, tcg_rd);
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}
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}
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}
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}
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