target/arm: Add aa64_va_parameters_both

We will want to check TBI for I and D simultaneously.

Backports commit e737ed2ad8c14b4b82ed241646ffa370d29d0937 from qemu

qemu/aarch64.h

@@ -3272,6 +3272,7 @@
 #define xscale_cpar_write xscale_cpar_write_aarch64
 #define ARM64_REGS_STORAGE_SIZE ARM64_REGS_STORAGE_SIZE_aarch64
 #define aa64_va_parameters aa64_va_parameters_aarch64
+#define aa64_va_parameters_both aa64_va_parameters_both_aarch64
 #define aarch64_cpu_do_interrupt aarch64_cpu_do_interrupt_aarch64
 #define aarch64_cpu_register_types aarch64_cpu_register_types_aarch64
 #define aarch64_sve_change_el aarch64_sve_change_el_aarch64

qemu/aarch64eb.h

@@ -3272,6 +3272,7 @@
 #define xscale_cpar_write xscale_cpar_write_aarch64eb
 #define ARM64_REGS_STORAGE_SIZE ARM64_REGS_STORAGE_SIZE_aarch64eb
 #define aa64_va_parameters aa64_va_parameters_aarch64eb
+#define aa64_va_parameters_both aa64_va_parameters_both_aarch64eb
 #define aarch64_cpu_do_interrupt aarch64_cpu_do_interrupt_aarch64eb
 #define aarch64_cpu_register_types aarch64_cpu_register_types_aarch64eb
 #define aarch64_sve_change_el aarch64_sve_change_el_aarch64eb

qemu/arm.h

@@ -3271,6 +3271,7 @@
 #define xscale_cp_reginfo xscale_cp_reginfo_arm
 #define xscale_cpar_write xscale_cpar_write_arm
 #define aa64_va_parameters aa64_va_parameters_arm
+#define aa64_va_parameters_both aa64_va_parameters_both_arm
 #define aarch64_translator_ops aarch64_translator_ops_arm
 #define arm_v7m_mmu_idx_for_secstate arm_v7m_mmu_idx_for_secstate_arm
 #define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_arm

qemu/armeb.h

@@ -3271,6 +3271,7 @@
 #define xscale_cp_reginfo xscale_cp_reginfo_armeb
 #define xscale_cpar_write xscale_cpar_write_armeb
 #define aa64_va_parameters aa64_va_parameters_armeb
+#define aa64_va_parameters_both aa64_va_parameters_both_armeb
 #define aarch64_translator_ops aarch64_translator_ops_armeb
 #define arm_v7m_mmu_idx_for_secstate arm_v7m_mmu_idx_for_secstate_armeb
 #define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_armeb

qemu/header_gen.py

@@ -3280,6 +3280,7 @@ symbols = (
 
 arm_symbols = (
     'aa64_va_parameters',
+    'aa64_va_parameters_both',
     'aarch64_translator_ops',
     'arm_v7m_mmu_idx_for_secstate',
     'arm_v7m_mmu_idx_for_secstate_and_priv',
@@ -3312,6 +3313,7 @@ arm_symbols = (
 aarch64_symbols = (
     'ARM64_REGS_STORAGE_SIZE',
     'aa64_va_parameters',
+    'aa64_va_parameters_both',
     'aarch64_cpu_do_interrupt',
     'aarch64_cpu_register_types',
     'aarch64_sve_change_el',

qemu/target/arm/helper.c

@@ -8948,8 +8948,8 @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
     return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint;
 }
 
-ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
+ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va,
-                                   ARMMMUIdx mmu_idx, bool data)
+                                        ARMMMUIdx mmu_idx)
 {
     uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
     uint32_t el = regime_el(env, mmu_idx);
@@ -9004,6 +9004,12 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
     return result;
 }
 
+ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
+                                   ARMMMUIdx mmu_idx, bool data)
+{
+    return aa64_va_parameters_both(env, va, mmu_idx);
+}
+
 static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
                                           ARMMMUIdx mmu_idx)
 {

qemu/target/arm/internals.h

@@ -959,9 +959,9 @@ typedef struct ARMVAParameters {
 } ARMVAParameters;
 
 #ifdef CONFIG_USER_ONLY
-static inline ARMVAParameters aa64_va_parameters(CPUARMState *env,
+static inline ARMVAParameters aa64_va_parameters_both(CPUARMState *env,
                                                       uint64_t va,
-                                                 ARMMMUIdx mmu_idx, bool data)
+                                                      ARMMMUIdx mmu_idx)
 {
     ARMVAParameters result = {0};
     /* 48-bit address space */
@@ -971,7 +971,16 @@ static inline ARMVAParameters aa64_va_parameters(CPUARMState *env,
 
     return result;
 }
+
+static inline ARMVAParameters aa64_va_parameters(CPUARMState *env,
+                                                 uint64_t va,
+                                                 ARMMMUIdx mmu_idx, bool data)
+{
+    return aa64_va_parameters_both(env, va, mmu_idx);
+}
 #else
+ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va,
+                                        ARMMMUIdx mmu_idx);
 ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
                                    ARMMMUIdx mmu_idx, bool data);
 #endif