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tcg: Add types and basic operations for host vectors

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Backports commit d2fd745fe8b9ac574d28b7ac63c39f6529749bd2 from qemu
This commit is contained in:
Richard Henderson 2018-03-06 11:49:50 -05:00 committed by Lioncash
parent 9ef32fc039
commit b9cd924fa5
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
45 changed files with 1009 additions and 5 deletions
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1
msvc/unicorn/aarch64-softmmu/aarch64-softmmu.vcxproj
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@ -76,6 +76,7 @@
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\optimize.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c" />
<ClCompile Include="..\..\..\qemu\translate-all.c" />
<ClCompile Include="..\..\..\qemu\translate-common.c" />

3
msvc/unicorn/aarch64-softmmu/aarch64-softmmu.vcxproj.filters
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@ -137,6 +137,9 @@
<ClCompile Include="..\..\..\qemu\tcg\tcg.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c">
<Filter>tcg</Filter>
</ClCompile>

1
msvc/unicorn/aarch64eb-softmmu/aarch64eb-softmmu.vcxproj
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@ -76,6 +76,7 @@
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\optimize.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c" />
<ClCompile Include="..\..\..\qemu\translate-all.c" />
<ClCompile Include="..\..\..\qemu\translate-common.c" />

3
msvc/unicorn/aarch64eb-softmmu/aarch64eb-softmmu.vcxproj.filters
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@ -137,6 +137,9 @@
<ClCompile Include="..\..\..\qemu\tcg\tcg.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c">
<Filter>tcg</Filter>
</ClCompile>

1
msvc/unicorn/arm-softmmu/arm-softmmu.vcxproj
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@ -72,6 +72,7 @@
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\optimize.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c" />
<ClCompile Include="..\..\..\qemu\translate-all.c" />
<ClCompile Include="..\..\..\qemu\translate-common.c" />

3
msvc/unicorn/arm-softmmu/arm-softmmu.vcxproj.filters
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@ -99,6 +99,9 @@
<ClCompile Include="..\..\..\qemu\tcg\tcg.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c">
<Filter>tcg</Filter>
</ClCompile>

1
msvc/unicorn/armeb-softmmu/armeb-softmmu.vcxproj
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@ -72,6 +72,7 @@
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\optimize.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c" />
<ClCompile Include="..\..\..\qemu\translate-all.c" />
<ClCompile Include="..\..\..\qemu\translate-common.c" />

3
msvc/unicorn/armeb-softmmu/armeb-softmmu.vcxproj.filters
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@ -125,6 +125,9 @@
<ClCompile Include="..\..\..\qemu\tcg\tcg.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c">
<Filter>tcg</Filter>
</ClCompile>

1
msvc/unicorn/m68k-softmmu/m68k-softmmu.vcxproj
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@ -55,6 +55,7 @@
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\optimize.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c" />
<ClCompile Include="..\..\..\qemu\translate-all.c" />
<ClCompile Include="..\..\..\qemu\translate-common.c" />

3
msvc/unicorn/m68k-softmmu/m68k-softmmu.vcxproj.filters
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@ -74,6 +74,9 @@
<ClCompile Include="..\..\..\qemu\tcg\tcg.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c">
<Filter>tcg</Filter>
</ClCompile>

1
msvc/unicorn/mips-softmmu/mips-softmmu.vcxproj
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@ -72,6 +72,7 @@
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\optimize.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c" />
<ClCompile Include="..\..\..\qemu\translate-all.c" />
<ClCompile Include="..\..\..\qemu\translate-common.c" />

3
msvc/unicorn/mips-softmmu/mips-softmmu.vcxproj.filters
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@ -84,6 +84,9 @@
<ClCompile Include="..\..\..\qemu\tcg\tcg.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c">
<Filter>tcg</Filter>
</ClCompile>

1
msvc/unicorn/mips64-softmmu/mips64-softmmu.vcxproj
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@ -72,6 +72,7 @@
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\optimize.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c" />
<ClCompile Include="..\..\..\qemu\translate-all.c" />
<ClCompile Include="..\..\..\qemu\translate-common.c" />

3
msvc/unicorn/mips64-softmmu/mips64-softmmu.vcxproj.filters
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@ -89,6 +89,9 @@
<ClCompile Include="..\..\..\qemu\tcg\tcg.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c">
<Filter>tcg</Filter>
</ClCompile>

1
msvc/unicorn/mips64el-softmmu/mips64el-softmmu.vcxproj
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@ -72,6 +72,7 @@
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\optimize.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c" />
<ClCompile Include="..\..\..\qemu\translate-all.c" />
<ClCompile Include="..\..\..\qemu\translate-common.c" />

3
msvc/unicorn/mips64el-softmmu/mips64el-softmmu.vcxproj.filters
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@ -90,6 +90,9 @@
<ClCompile Include="..\..\..\qemu\tcg\tcg.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c">
<Filter>tcg</Filter>
</ClCompile>

1
msvc/unicorn/mipsel-softmmu/mipsel-softmmu.vcxproj
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@ -72,6 +72,7 @@
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\optimize.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c" />
<ClCompile Include="..\..\..\qemu\translate-all.c" />
<ClCompile Include="..\..\..\qemu\translate-common.c" />

3
msvc/unicorn/mipsel-softmmu/mipsel-softmmu.vcxproj.filters
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@ -88,6 +88,9 @@
<ClCompile Include="..\..\..\qemu\tcg\tcg.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c">
<Filter>tcg</Filter>
</ClCompile>

1
msvc/unicorn/sparc-softmmu/sparc-softmmu.vcxproj
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@ -66,6 +66,7 @@
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\optimize.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c" />
<ClCompile Include="..\..\..\qemu\translate-all.c" />
<ClCompile Include="..\..\..\qemu\translate-common.c" />

3
msvc/unicorn/sparc-softmmu/sparc-softmmu.vcxproj.filters
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@ -74,6 +74,9 @@
<ClCompile Include="..\..\..\qemu\tcg\tcg.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c">
<Filter>tcg</Filter>
</ClCompile>

1
msvc/unicorn/sparc64-softmmu/sparc64-softmmu.vcxproj
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@ -67,6 +67,7 @@
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\optimize.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c" />
<ClCompile Include="..\..\..\qemu\translate-all.c" />
<ClCompile Include="..\..\..\qemu\translate-common.c" />

3
msvc/unicorn/sparc64-softmmu/sparc64-softmmu.vcxproj.filters
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@ -107,6 +107,9 @@
<ClCompile Include="..\..\..\qemu\tcg\tcg.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c">
<Filter>tcg</Filter>
</ClCompile>

1
msvc/unicorn/x86_64-softmmu/x86_64-softmmu.vcxproj
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@ -80,6 +80,7 @@
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\optimize.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c" />
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c" />
<ClCompile Include="..\..\..\qemu\translate-all.c" />
<ClCompile Include="..\..\..\qemu\translate-common.c" />

3
msvc/unicorn/x86_64-softmmu/x86_64-softmmu.vcxproj.filters
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@ -159,6 +159,9 @@
<ClCompile Include="..\..\..\qemu\tcg\tcg.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-op-vec.c">
<Filter>tcg</Filter>
</ClCompile>
<ClCompile Include="..\..\..\qemu\tcg\tcg-common.c">
<Filter>tcg</Filter>
</ClCompile>

4
qemu/Makefile.target
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@ -43,8 +43,8 @@ all: $(PROGS)
obj-y = exec.o translate-all.o cpu-exec.o
obj-y += translate-common.o
obj-y += cpu-exec-common.o
obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-op.o tcg/optimize.o
obj-$(CONFIG_TCG) += tcg/tcg-common.o
obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-op.o tcg/tcg-op-vec.o
obj-$(CONFIG_TCG) += tcg/tcg-common.o tcg/optimize.o
obj-y += fpu/softfloat.o
obj-y += target/$(TARGET_BASE_ARCH)/
obj-y += tcg-runtime.o

30
qemu/aarch64.h
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@ -2971,6 +2971,10 @@
#define tcg_const_i64 tcg_const_i64_aarch64
#define tcg_const_local_i32 tcg_const_local_i32_aarch64
#define tcg_const_local_i64 tcg_const_local_i64_aarch64
#define tcg_const_ones_vec tcg_const_ones_vec_aarch64
#define tcg_const_ones_vec_matching tcg_const_ones_vec_matching_aarch64
#define tcg_const_zeros_vec tcg_const_zeros_vec_aarch64
#define tcg_const_zeros_vec_matching tcg_const_zeros_vec_matching_aarch64
#define tcg_constant_folding tcg_constant_folding_aarch64
#define tcg_context_init tcg_context_init_aarch64
#define tcg_cpu_exec tcg_cpu_exec_aarch64
@ -2989,12 +2993,15 @@
#define tcg_gen_add2_i64 tcg_gen_add2_i64_aarch64
#define tcg_gen_add_i32 tcg_gen_add_i32_aarch64
#define tcg_gen_add_i64 tcg_gen_add_i64_aarch64
#define tcg_gen_add_vec tcg_gen_add_vec_aarch64
#define tcg_gen_addi_i32 tcg_gen_addi_i32_aarch64
#define tcg_gen_addi_i64 tcg_gen_addi_i64_aarch64
#define tcg_gen_and_i32 tcg_gen_and_i32_aarch64
#define tcg_gen_and_i64 tcg_gen_and_i64_aarch64
#define tcg_gen_and_vec tcg_gen_and_vec_aarch64
#define tcg_gen_andc_i32 tcg_gen_andc_i32_aarch64
#define tcg_gen_andc_i64 tcg_gen_andc_i64_aarch64
#define tcg_gen_andc_vec tcg_gen_andc_vec_aarch64
#define tcg_gen_andi_i32 tcg_gen_andi_i32_aarch64
#define tcg_gen_andi_i64 tcg_gen_andi_i64_aarch64
#define tcg_gen_atomic_add_fetch_i32 tcg_gen_atomic_add_fetch_i32_aarch64
@ -3051,6 +3058,12 @@
#define tcg_gen_div_i64 tcg_gen_div_i64_aarch64
#define tcg_gen_divu_i32 tcg_gen_divu_i32_aarch64
#define tcg_gen_divu_i64 tcg_gen_divu_i64_aarch64
#define tcg_gen_dup8i_vec tcg_gen_dup8i_vec_aarch64
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_aarch64
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_aarch64
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_aarch64
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_aarch64
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_aarch64
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_aarch64
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_aarch64
#define tcg_gen_exit_tb tcg_gen_exit_tb_aarch64
@ -3082,12 +3095,14 @@
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_aarch64
#define tcg_gen_ld_i32 tcg_gen_ld_i32_aarch64
#define tcg_gen_ld_i64 tcg_gen_ld_i64_aarch64
#define tcg_gen_ld_vec tcg_gen_ld_vec_aarch64
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_aarch64
#define tcg_gen_ldst_op_i64 tcg_gen_ldst_op_i64_aarch64
#define tcg_gen_lookup_and_goto_ptr tcg_gen_lookup_and_goto_ptr_aarch64
#define tcg_gen_mb tcg_gen_mb_aarch64
#define tcg_gen_mov_i32 tcg_gen_mov_i32_aarch64
#define tcg_gen_mov_i64 tcg_gen_mov_i64_aarch64
#define tcg_gen_mov_vec tcg_gen_mov_vec_aarch64
#define tcg_gen_movcond_i32 tcg_gen_movcond_i32_aarch64
#define tcg_gen_movcond_i64 tcg_gen_movcond_i64_aarch64
#define tcg_gen_movi_i32 tcg_gen_movi_i32_aarch64
@ -3106,10 +3121,13 @@
#define tcg_gen_nand_i64 tcg_gen_nand_i64_aarch64
#define tcg_gen_neg_i32 tcg_gen_neg_i32_aarch64
#define tcg_gen_neg_i64 tcg_gen_neg_i64_aarch64
#define tcg_gen_neg_vec tcg_gen_neg_vec_aarch64
#define tcg_gen_nor_i32 tcg_gen_nor_i32_aarch64
#define tcg_gen_nor_i64 tcg_gen_nor_i64_aarch64
#define tcg_gen_nor_vec tcg_gen_nor_vec_aarch64
#define tcg_gen_not_i32 tcg_gen_not_i32_aarch64
#define tcg_gen_not_i64 tcg_gen_not_i64_aarch64
#define tcg_gen_not_vec tcg_gen_not_vec_aarch64
#define tcg_gen_op1 tcg_gen_op1_aarch64
#define tcg_gen_op1i tcg_gen_op1i_aarch64
#define tcg_gen_op2 tcg_gen_op2_aarch64
@ -3133,8 +3151,10 @@
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_aarch64
#define tcg_gen_or_i32 tcg_gen_or_i32_aarch64
#define tcg_gen_or_i64 tcg_gen_or_i64_aarch64
#define tcg_gen_or_vec tcg_gen_or_vec_aarch64
#define tcg_gen_orc_i32 tcg_gen_orc_i32_aarch64
#define tcg_gen_orc_i64 tcg_gen_orc_i64_aarch64
#define tcg_gen_orc_vec tcg_gen_orc_vec_aarch64
#define tcg_gen_ori_i32 tcg_gen_ori_i32_aarch64
#define tcg_gen_ori_i64 tcg_gen_ori_i64_aarch64
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_aarch64
@ -3174,16 +3194,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_aarch64
#define tcg_gen_st_i32 tcg_gen_st_i32_aarch64
#define tcg_gen_st_i64 tcg_gen_st_i64_aarch64
#define tcg_gen_st_vec tcg_gen_st_vec_aarch64
#define tcg_gen_stl_vec tcg_gen_stl_vec_aarch64
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_aarch64
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_aarch64
#define tcg_gen_sub_i32 tcg_gen_sub_i32_aarch64
#define tcg_gen_sub_i64 tcg_gen_sub_i64_aarch64
#define tcg_gen_sub_vec tcg_gen_sub_vec_aarch64
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_aarch64
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_aarch64
#define tcg_gen_subi_i32 tcg_gen_subi_i32_aarch64
#define tcg_gen_subi_i64 tcg_gen_subi_i64_aarch64
#define tcg_gen_xor_i32 tcg_gen_xor_i32_aarch64
#define tcg_gen_xor_i64 tcg_gen_xor_i64_aarch64
#define tcg_gen_xor_vec tcg_gen_xor_vec_aarch64
#define tcg_gen_xori_i32 tcg_gen_xori_i32_aarch64
#define tcg_gen_xori_i64 tcg_gen_xori_i64_aarch64
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_aarch64
@ -3290,6 +3314,7 @@
#define tcg_temp_alloc tcg_temp_alloc_aarch64
#define tcg_temp_free_i32 tcg_temp_free_i32_aarch64
#define tcg_temp_free_i64 tcg_temp_free_i64_aarch64
#define tcg_temp_free_vec tcg_temp_free_vec_aarch64
#define tcg_temp_free_internal tcg_temp_free_internal_aarch64
#define tcg_temp_local_new_i32 tcg_temp_local_new_i32_aarch64
#define tcg_temp_local_new_i64 tcg_temp_local_new_i64_aarch64
@ -3298,6 +3323,8 @@
#define tcg_temp_new_internal tcg_temp_new_internal_aarch64
#define tcg_temp_new_internal_i32 tcg_temp_new_internal_i32_aarch64
#define tcg_temp_new_internal_i64 tcg_temp_new_internal_i64_aarch64
#define tcg_temp_new_vec tcg_temp_new_vec_aarch64
#define tcg_temp_new_vec_matching tcg_temp_new_vec_matching_aarch64
#define tdb_hash tdb_hash_aarch64
#define teecr_write teecr_write_aarch64
#define teehbr_access teehbr_access_aarch64
@ -3395,6 +3422,9 @@
#define v8_el3_no_el2_cp_reginfo v8_el3_no_el2_cp_reginfo_aarch64
#define vapa_cp_reginfo vapa_cp_reginfo_aarch64
#define vbar_write vbar_write_aarch64
#define vec_gen_2 vec_gen_2_aarch64
#define vec_gen_3 vec_gen_3_aarch64
#define vec_gen_4 vec_gen_4_aarch64
#define vfp_exceptbits_from_host vfp_exceptbits_from_host_aarch64
#define vfp_exceptbits_to_host vfp_exceptbits_to_host_aarch64
#define vfp_get_fpcr vfp_get_fpcr_aarch64

30
qemu/aarch64eb.h
View file

@ -2971,6 +2971,10 @@
#define tcg_const_i64 tcg_const_i64_aarch64eb
#define tcg_const_local_i32 tcg_const_local_i32_aarch64eb
#define tcg_const_local_i64 tcg_const_local_i64_aarch64eb
#define tcg_const_ones_vec tcg_const_ones_vec_aarch64eb
#define tcg_const_ones_vec_matching tcg_const_ones_vec_matching_aarch64eb
#define tcg_const_zeros_vec tcg_const_zeros_vec_aarch64eb
#define tcg_const_zeros_vec_matching tcg_const_zeros_vec_matching_aarch64eb
#define tcg_constant_folding tcg_constant_folding_aarch64eb
#define tcg_context_init tcg_context_init_aarch64eb
#define tcg_cpu_exec tcg_cpu_exec_aarch64eb
@ -2989,12 +2993,15 @@
#define tcg_gen_add2_i64 tcg_gen_add2_i64_aarch64eb
#define tcg_gen_add_i32 tcg_gen_add_i32_aarch64eb
#define tcg_gen_add_i64 tcg_gen_add_i64_aarch64eb
#define tcg_gen_add_vec tcg_gen_add_vec_aarch64eb
#define tcg_gen_addi_i32 tcg_gen_addi_i32_aarch64eb
#define tcg_gen_addi_i64 tcg_gen_addi_i64_aarch64eb
#define tcg_gen_and_i32 tcg_gen_and_i32_aarch64eb
#define tcg_gen_and_i64 tcg_gen_and_i64_aarch64eb
#define tcg_gen_and_vec tcg_gen_and_vec_aarch64eb
#define tcg_gen_andc_i32 tcg_gen_andc_i32_aarch64eb
#define tcg_gen_andc_i64 tcg_gen_andc_i64_aarch64eb
#define tcg_gen_andc_vec tcg_gen_andc_vec_aarch64eb
#define tcg_gen_andi_i32 tcg_gen_andi_i32_aarch64eb
#define tcg_gen_andi_i64 tcg_gen_andi_i64_aarch64eb
#define tcg_gen_atomic_add_fetch_i32 tcg_gen_atomic_add_fetch_i32_aarch64eb
@ -3051,6 +3058,12 @@
#define tcg_gen_div_i64 tcg_gen_div_i64_aarch64eb
#define tcg_gen_divu_i32 tcg_gen_divu_i32_aarch64eb
#define tcg_gen_divu_i64 tcg_gen_divu_i64_aarch64eb
#define tcg_gen_dup8i_vec tcg_gen_dup8i_vec_aarch64eb
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_aarch64eb
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_aarch64eb
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_aarch64eb
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_aarch64eb
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_aarch64eb
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_aarch64eb
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_aarch64eb
#define tcg_gen_exit_tb tcg_gen_exit_tb_aarch64eb
@ -3082,12 +3095,14 @@
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_aarch64eb
#define tcg_gen_ld_i32 tcg_gen_ld_i32_aarch64eb
#define tcg_gen_ld_i64 tcg_gen_ld_i64_aarch64eb
#define tcg_gen_ld_vec tcg_gen_ld_vec_aarch64eb
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_aarch64eb
#define tcg_gen_ldst_op_i64 tcg_gen_ldst_op_i64_aarch64eb
#define tcg_gen_lookup_and_goto_ptr tcg_gen_lookup_and_goto_ptr_aarch64eb
#define tcg_gen_mb tcg_gen_mb_aarch64eb
#define tcg_gen_mov_i32 tcg_gen_mov_i32_aarch64eb
#define tcg_gen_mov_i64 tcg_gen_mov_i64_aarch64eb
#define tcg_gen_mov_vec tcg_gen_mov_vec_aarch64eb
#define tcg_gen_movcond_i32 tcg_gen_movcond_i32_aarch64eb
#define tcg_gen_movcond_i64 tcg_gen_movcond_i64_aarch64eb
#define tcg_gen_movi_i32 tcg_gen_movi_i32_aarch64eb
@ -3106,10 +3121,13 @@
#define tcg_gen_nand_i64 tcg_gen_nand_i64_aarch64eb
#define tcg_gen_neg_i32 tcg_gen_neg_i32_aarch64eb
#define tcg_gen_neg_i64 tcg_gen_neg_i64_aarch64eb
#define tcg_gen_neg_vec tcg_gen_neg_vec_aarch64eb
#define tcg_gen_nor_i32 tcg_gen_nor_i32_aarch64eb
#define tcg_gen_nor_i64 tcg_gen_nor_i64_aarch64eb
#define tcg_gen_nor_vec tcg_gen_nor_vec_aarch64eb
#define tcg_gen_not_i32 tcg_gen_not_i32_aarch64eb
#define tcg_gen_not_i64 tcg_gen_not_i64_aarch64eb
#define tcg_gen_not_vec tcg_gen_not_vec_aarch64eb
#define tcg_gen_op1 tcg_gen_op1_aarch64eb
#define tcg_gen_op1i tcg_gen_op1i_aarch64eb
#define tcg_gen_op2 tcg_gen_op2_aarch64eb
@ -3133,8 +3151,10 @@
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_aarch64eb
#define tcg_gen_or_i32 tcg_gen_or_i32_aarch64eb
#define tcg_gen_or_i64 tcg_gen_or_i64_aarch64eb
#define tcg_gen_or_vec tcg_gen_or_vec_aarch64eb
#define tcg_gen_orc_i32 tcg_gen_orc_i32_aarch64eb
#define tcg_gen_orc_i64 tcg_gen_orc_i64_aarch64eb
#define tcg_gen_orc_vec tcg_gen_orc_vec_aarch64eb
#define tcg_gen_ori_i32 tcg_gen_ori_i32_aarch64eb
#define tcg_gen_ori_i64 tcg_gen_ori_i64_aarch64eb
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_aarch64eb
@ -3174,16 +3194,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_aarch64eb
#define tcg_gen_st_i32 tcg_gen_st_i32_aarch64eb
#define tcg_gen_st_i64 tcg_gen_st_i64_aarch64eb
#define tcg_gen_st_vec tcg_gen_st_vec_aarch64eb
#define tcg_gen_stl_vec tcg_gen_stl_vec_aarch64eb
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_aarch64eb
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_aarch64eb
#define tcg_gen_sub_i32 tcg_gen_sub_i32_aarch64eb
#define tcg_gen_sub_i64 tcg_gen_sub_i64_aarch64eb
#define tcg_gen_sub_vec tcg_gen_sub_vec_aarch64eb
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_aarch64eb
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_aarch64eb
#define tcg_gen_subi_i32 tcg_gen_subi_i32_aarch64eb
#define tcg_gen_subi_i64 tcg_gen_subi_i64_aarch64eb
#define tcg_gen_xor_i32 tcg_gen_xor_i32_aarch64eb
#define tcg_gen_xor_i64 tcg_gen_xor_i64_aarch64eb
#define tcg_gen_xor_vec tcg_gen_xor_vec_aarch64eb
#define tcg_gen_xori_i32 tcg_gen_xori_i32_aarch64eb
#define tcg_gen_xori_i64 tcg_gen_xori_i64_aarch64eb
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_aarch64eb
@ -3290,6 +3314,7 @@
#define tcg_temp_alloc tcg_temp_alloc_aarch64eb
#define tcg_temp_free_i32 tcg_temp_free_i32_aarch64eb
#define tcg_temp_free_i64 tcg_temp_free_i64_aarch64eb
#define tcg_temp_free_vec tcg_temp_free_vec_aarch64eb
#define tcg_temp_free_internal tcg_temp_free_internal_aarch64eb
#define tcg_temp_local_new_i32 tcg_temp_local_new_i32_aarch64eb
#define tcg_temp_local_new_i64 tcg_temp_local_new_i64_aarch64eb
@ -3298,6 +3323,8 @@
#define tcg_temp_new_internal tcg_temp_new_internal_aarch64eb
#define tcg_temp_new_internal_i32 tcg_temp_new_internal_i32_aarch64eb
#define tcg_temp_new_internal_i64 tcg_temp_new_internal_i64_aarch64eb
#define tcg_temp_new_vec tcg_temp_new_vec_aarch64eb
#define tcg_temp_new_vec_matching tcg_temp_new_vec_matching_aarch64eb
#define tdb_hash tdb_hash_aarch64eb
#define teecr_write teecr_write_aarch64eb
#define teehbr_access teehbr_access_aarch64eb
@ -3395,6 +3422,9 @@
#define v8_el3_no_el2_cp_reginfo v8_el3_no_el2_cp_reginfo_aarch64eb
#define vapa_cp_reginfo vapa_cp_reginfo_aarch64eb
#define vbar_write vbar_write_aarch64eb
#define vec_gen_2 vec_gen_2_aarch64eb
#define vec_gen_3 vec_gen_3_aarch64eb
#define vec_gen_4 vec_gen_4_aarch64eb
#define vfp_exceptbits_from_host vfp_exceptbits_from_host_aarch64eb
#define vfp_exceptbits_to_host vfp_exceptbits_to_host_aarch64eb
#define vfp_get_fpcr vfp_get_fpcr_aarch64eb

30
qemu/arm.h
View file

@ -2971,6 +2971,10 @@
#define tcg_const_i64 tcg_const_i64_arm
#define tcg_const_local_i32 tcg_const_local_i32_arm
#define tcg_const_local_i64 tcg_const_local_i64_arm
#define tcg_const_ones_vec tcg_const_ones_vec_arm
#define tcg_const_ones_vec_matching tcg_const_ones_vec_matching_arm
#define tcg_const_zeros_vec tcg_const_zeros_vec_arm
#define tcg_const_zeros_vec_matching tcg_const_zeros_vec_matching_arm
#define tcg_constant_folding tcg_constant_folding_arm
#define tcg_context_init tcg_context_init_arm
#define tcg_cpu_exec tcg_cpu_exec_arm
@ -2989,12 +2993,15 @@
#define tcg_gen_add2_i64 tcg_gen_add2_i64_arm
#define tcg_gen_add_i32 tcg_gen_add_i32_arm
#define tcg_gen_add_i64 tcg_gen_add_i64_arm
#define tcg_gen_add_vec tcg_gen_add_vec_arm
#define tcg_gen_addi_i32 tcg_gen_addi_i32_arm
#define tcg_gen_addi_i64 tcg_gen_addi_i64_arm
#define tcg_gen_and_i32 tcg_gen_and_i32_arm
#define tcg_gen_and_i64 tcg_gen_and_i64_arm
#define tcg_gen_and_vec tcg_gen_and_vec_arm
#define tcg_gen_andc_i32 tcg_gen_andc_i32_arm
#define tcg_gen_andc_i64 tcg_gen_andc_i64_arm
#define tcg_gen_andc_vec tcg_gen_andc_vec_arm
#define tcg_gen_andi_i32 tcg_gen_andi_i32_arm
#define tcg_gen_andi_i64 tcg_gen_andi_i64_arm
#define tcg_gen_atomic_add_fetch_i32 tcg_gen_atomic_add_fetch_i32_arm
@ -3051,6 +3058,12 @@
#define tcg_gen_div_i64 tcg_gen_div_i64_arm
#define tcg_gen_divu_i32 tcg_gen_divu_i32_arm
#define tcg_gen_divu_i64 tcg_gen_divu_i64_arm
#define tcg_gen_dup8i_vec tcg_gen_dup8i_vec_arm
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_arm
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_arm
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_arm
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_arm
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_arm
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_arm
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_arm
#define tcg_gen_exit_tb tcg_gen_exit_tb_arm
@ -3082,12 +3095,14 @@
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_arm
#define tcg_gen_ld_i32 tcg_gen_ld_i32_arm
#define tcg_gen_ld_i64 tcg_gen_ld_i64_arm
#define tcg_gen_ld_vec tcg_gen_ld_vec_arm
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_arm
#define tcg_gen_ldst_op_i64 tcg_gen_ldst_op_i64_arm
#define tcg_gen_lookup_and_goto_ptr tcg_gen_lookup_and_goto_ptr_arm
#define tcg_gen_mb tcg_gen_mb_arm
#define tcg_gen_mov_i32 tcg_gen_mov_i32_arm
#define tcg_gen_mov_i64 tcg_gen_mov_i64_arm
#define tcg_gen_mov_vec tcg_gen_mov_vec_arm
#define tcg_gen_movcond_i32 tcg_gen_movcond_i32_arm
#define tcg_gen_movcond_i64 tcg_gen_movcond_i64_arm
#define tcg_gen_movi_i32 tcg_gen_movi_i32_arm
@ -3106,10 +3121,13 @@
#define tcg_gen_nand_i64 tcg_gen_nand_i64_arm
#define tcg_gen_neg_i32 tcg_gen_neg_i32_arm
#define tcg_gen_neg_i64 tcg_gen_neg_i64_arm
#define tcg_gen_neg_vec tcg_gen_neg_vec_arm
#define tcg_gen_nor_i32 tcg_gen_nor_i32_arm
#define tcg_gen_nor_i64 tcg_gen_nor_i64_arm
#define tcg_gen_nor_vec tcg_gen_nor_vec_arm
#define tcg_gen_not_i32 tcg_gen_not_i32_arm
#define tcg_gen_not_i64 tcg_gen_not_i64_arm
#define tcg_gen_not_vec tcg_gen_not_vec_arm
#define tcg_gen_op1 tcg_gen_op1_arm
#define tcg_gen_op1i tcg_gen_op1i_arm
#define tcg_gen_op2 tcg_gen_op2_arm
@ -3133,8 +3151,10 @@
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_arm
#define tcg_gen_or_i32 tcg_gen_or_i32_arm
#define tcg_gen_or_i64 tcg_gen_or_i64_arm
#define tcg_gen_or_vec tcg_gen_or_vec_arm
#define tcg_gen_orc_i32 tcg_gen_orc_i32_arm
#define tcg_gen_orc_i64 tcg_gen_orc_i64_arm
#define tcg_gen_orc_vec tcg_gen_orc_vec_arm
#define tcg_gen_ori_i32 tcg_gen_ori_i32_arm
#define tcg_gen_ori_i64 tcg_gen_ori_i64_arm
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_arm
@ -3174,16 +3194,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_arm
#define tcg_gen_st_i32 tcg_gen_st_i32_arm
#define tcg_gen_st_i64 tcg_gen_st_i64_arm
#define tcg_gen_st_vec tcg_gen_st_vec_arm
#define tcg_gen_stl_vec tcg_gen_stl_vec_arm
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_arm
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_arm
#define tcg_gen_sub_i32 tcg_gen_sub_i32_arm
#define tcg_gen_sub_i64 tcg_gen_sub_i64_arm
#define tcg_gen_sub_vec tcg_gen_sub_vec_arm
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_arm
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_arm
#define tcg_gen_subi_i32 tcg_gen_subi_i32_arm
#define tcg_gen_subi_i64 tcg_gen_subi_i64_arm
#define tcg_gen_xor_i32 tcg_gen_xor_i32_arm
#define tcg_gen_xor_i64 tcg_gen_xor_i64_arm
#define tcg_gen_xor_vec tcg_gen_xor_vec_arm
#define tcg_gen_xori_i32 tcg_gen_xori_i32_arm
#define tcg_gen_xori_i64 tcg_gen_xori_i64_arm
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_arm
@ -3290,6 +3314,7 @@
#define tcg_temp_alloc tcg_temp_alloc_arm
#define tcg_temp_free_i32 tcg_temp_free_i32_arm
#define tcg_temp_free_i64 tcg_temp_free_i64_arm
#define tcg_temp_free_vec tcg_temp_free_vec_arm
#define tcg_temp_free_internal tcg_temp_free_internal_arm
#define tcg_temp_local_new_i32 tcg_temp_local_new_i32_arm
#define tcg_temp_local_new_i64 tcg_temp_local_new_i64_arm
@ -3298,6 +3323,8 @@
#define tcg_temp_new_internal tcg_temp_new_internal_arm
#define tcg_temp_new_internal_i32 tcg_temp_new_internal_i32_arm
#define tcg_temp_new_internal_i64 tcg_temp_new_internal_i64_arm
#define tcg_temp_new_vec tcg_temp_new_vec_arm
#define tcg_temp_new_vec_matching tcg_temp_new_vec_matching_arm
#define tdb_hash tdb_hash_arm
#define teecr_write teecr_write_arm
#define teehbr_access teehbr_access_arm
@ -3395,6 +3422,9 @@
#define v8_el3_no_el2_cp_reginfo v8_el3_no_el2_cp_reginfo_arm
#define vapa_cp_reginfo vapa_cp_reginfo_arm
#define vbar_write vbar_write_arm
#define vec_gen_2 vec_gen_2_arm
#define vec_gen_3 vec_gen_3_arm
#define vec_gen_4 vec_gen_4_arm
#define vfp_exceptbits_from_host vfp_exceptbits_from_host_arm
#define vfp_exceptbits_to_host vfp_exceptbits_to_host_arm
#define vfp_get_fpcr vfp_get_fpcr_arm

30
qemu/armeb.h
View file

@ -2971,6 +2971,10 @@
#define tcg_const_i64 tcg_const_i64_armeb
#define tcg_const_local_i32 tcg_const_local_i32_armeb
#define tcg_const_local_i64 tcg_const_local_i64_armeb
#define tcg_const_ones_vec tcg_const_ones_vec_armeb
#define tcg_const_ones_vec_matching tcg_const_ones_vec_matching_armeb
#define tcg_const_zeros_vec tcg_const_zeros_vec_armeb
#define tcg_const_zeros_vec_matching tcg_const_zeros_vec_matching_armeb
#define tcg_constant_folding tcg_constant_folding_armeb
#define tcg_context_init tcg_context_init_armeb
#define tcg_cpu_exec tcg_cpu_exec_armeb
@ -2989,12 +2993,15 @@
#define tcg_gen_add2_i64 tcg_gen_add2_i64_armeb
#define tcg_gen_add_i32 tcg_gen_add_i32_armeb
#define tcg_gen_add_i64 tcg_gen_add_i64_armeb
#define tcg_gen_add_vec tcg_gen_add_vec_armeb
#define tcg_gen_addi_i32 tcg_gen_addi_i32_armeb
#define tcg_gen_addi_i64 tcg_gen_addi_i64_armeb
#define tcg_gen_and_i32 tcg_gen_and_i32_armeb
#define tcg_gen_and_i64 tcg_gen_and_i64_armeb
#define tcg_gen_and_vec tcg_gen_and_vec_armeb
#define tcg_gen_andc_i32 tcg_gen_andc_i32_armeb
#define tcg_gen_andc_i64 tcg_gen_andc_i64_armeb
#define tcg_gen_andc_vec tcg_gen_andc_vec_armeb
#define tcg_gen_andi_i32 tcg_gen_andi_i32_armeb
#define tcg_gen_andi_i64 tcg_gen_andi_i64_armeb
#define tcg_gen_atomic_add_fetch_i32 tcg_gen_atomic_add_fetch_i32_armeb
@ -3051,6 +3058,12 @@
#define tcg_gen_div_i64 tcg_gen_div_i64_armeb
#define tcg_gen_divu_i32 tcg_gen_divu_i32_armeb
#define tcg_gen_divu_i64 tcg_gen_divu_i64_armeb
#define tcg_gen_dup8i_vec tcg_gen_dup8i_vec_armeb
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_armeb
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_armeb
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_armeb
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_armeb
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_armeb
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_armeb
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_armeb
#define tcg_gen_exit_tb tcg_gen_exit_tb_armeb
@ -3082,12 +3095,14 @@
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_armeb
#define tcg_gen_ld_i32 tcg_gen_ld_i32_armeb
#define tcg_gen_ld_i64 tcg_gen_ld_i64_armeb
#define tcg_gen_ld_vec tcg_gen_ld_vec_armeb
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_armeb
#define tcg_gen_ldst_op_i64 tcg_gen_ldst_op_i64_armeb
#define tcg_gen_lookup_and_goto_ptr tcg_gen_lookup_and_goto_ptr_armeb
#define tcg_gen_mb tcg_gen_mb_armeb
#define tcg_gen_mov_i32 tcg_gen_mov_i32_armeb
#define tcg_gen_mov_i64 tcg_gen_mov_i64_armeb
#define tcg_gen_mov_vec tcg_gen_mov_vec_armeb
#define tcg_gen_movcond_i32 tcg_gen_movcond_i32_armeb
#define tcg_gen_movcond_i64 tcg_gen_movcond_i64_armeb
#define tcg_gen_movi_i32 tcg_gen_movi_i32_armeb
@ -3106,10 +3121,13 @@
#define tcg_gen_nand_i64 tcg_gen_nand_i64_armeb
#define tcg_gen_neg_i32 tcg_gen_neg_i32_armeb
#define tcg_gen_neg_i64 tcg_gen_neg_i64_armeb
#define tcg_gen_neg_vec tcg_gen_neg_vec_armeb
#define tcg_gen_nor_i32 tcg_gen_nor_i32_armeb
#define tcg_gen_nor_i64 tcg_gen_nor_i64_armeb
#define tcg_gen_nor_vec tcg_gen_nor_vec_armeb
#define tcg_gen_not_i32 tcg_gen_not_i32_armeb
#define tcg_gen_not_i64 tcg_gen_not_i64_armeb
#define tcg_gen_not_vec tcg_gen_not_vec_armeb
#define tcg_gen_op1 tcg_gen_op1_armeb
#define tcg_gen_op1i tcg_gen_op1i_armeb
#define tcg_gen_op2 tcg_gen_op2_armeb
@ -3133,8 +3151,10 @@
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_armeb
#define tcg_gen_or_i32 tcg_gen_or_i32_armeb
#define tcg_gen_or_i64 tcg_gen_or_i64_armeb
#define tcg_gen_or_vec tcg_gen_or_vec_armeb
#define tcg_gen_orc_i32 tcg_gen_orc_i32_armeb
#define tcg_gen_orc_i64 tcg_gen_orc_i64_armeb
#define tcg_gen_orc_vec tcg_gen_orc_vec_armeb
#define tcg_gen_ori_i32 tcg_gen_ori_i32_armeb
#define tcg_gen_ori_i64 tcg_gen_ori_i64_armeb
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_armeb
@ -3174,16 +3194,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_armeb
#define tcg_gen_st_i32 tcg_gen_st_i32_armeb
#define tcg_gen_st_i64 tcg_gen_st_i64_armeb
#define tcg_gen_st_vec tcg_gen_st_vec_armeb
#define tcg_gen_stl_vec tcg_gen_stl_vec_armeb
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_armeb
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_armeb
#define tcg_gen_sub_i32 tcg_gen_sub_i32_armeb
#define tcg_gen_sub_i64 tcg_gen_sub_i64_armeb
#define tcg_gen_sub_vec tcg_gen_sub_vec_armeb
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_armeb
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_armeb
#define tcg_gen_subi_i32 tcg_gen_subi_i32_armeb
#define tcg_gen_subi_i64 tcg_gen_subi_i64_armeb
#define tcg_gen_xor_i32 tcg_gen_xor_i32_armeb
#define tcg_gen_xor_i64 tcg_gen_xor_i64_armeb
#define tcg_gen_xor_vec tcg_gen_xor_vec_armeb
#define tcg_gen_xori_i32 tcg_gen_xori_i32_armeb
#define tcg_gen_xori_i64 tcg_gen_xori_i64_armeb
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_armeb
@ -3290,6 +3314,7 @@
#define tcg_temp_alloc tcg_temp_alloc_armeb
#define tcg_temp_free_i32 tcg_temp_free_i32_armeb
#define tcg_temp_free_i64 tcg_temp_free_i64_armeb
#define tcg_temp_free_vec tcg_temp_free_vec_armeb
#define tcg_temp_free_internal tcg_temp_free_internal_armeb
#define tcg_temp_local_new_i32 tcg_temp_local_new_i32_armeb
#define tcg_temp_local_new_i64 tcg_temp_local_new_i64_armeb
@ -3298,6 +3323,8 @@
#define tcg_temp_new_internal tcg_temp_new_internal_armeb
#define tcg_temp_new_internal_i32 tcg_temp_new_internal_i32_armeb
#define tcg_temp_new_internal_i64 tcg_temp_new_internal_i64_armeb
#define tcg_temp_new_vec tcg_temp_new_vec_armeb
#define tcg_temp_new_vec_matching tcg_temp_new_vec_matching_armeb
#define tdb_hash tdb_hash_armeb
#define teecr_write teecr_write_armeb
#define teehbr_access teehbr_access_armeb
@ -3395,6 +3422,9 @@
#define v8_el3_no_el2_cp_reginfo v8_el3_no_el2_cp_reginfo_armeb
#define vapa_cp_reginfo vapa_cp_reginfo_armeb
#define vbar_write vbar_write_armeb
#define vec_gen_2 vec_gen_2_armeb
#define vec_gen_3 vec_gen_3_armeb
#define vec_gen_4 vec_gen_4_armeb
#define vfp_exceptbits_from_host vfp_exceptbits_from_host_armeb
#define vfp_exceptbits_to_host vfp_exceptbits_to_host_armeb
#define vfp_get_fpcr vfp_get_fpcr_armeb

30
qemu/header_gen.py
View file

@ -2977,6 +2977,10 @@ symbols = (
'tcg_const_i64',
'tcg_const_local_i32',
'tcg_const_local_i64',
'tcg_const_ones_vec',
'tcg_const_ones_vec_matching',
'tcg_const_zeros_vec',
'tcg_const_zeros_vec_matching',
'tcg_constant_folding',
'tcg_context_init',
'tcg_cpu_exec',
@ -2995,12 +2999,15 @@ symbols = (
'tcg_gen_add2_i64',
'tcg_gen_add_i32',
'tcg_gen_add_i64',
'tcg_gen_add_vec',
'tcg_gen_addi_i32',
'tcg_gen_addi_i64',
'tcg_gen_and_i32',
'tcg_gen_and_i64',
'tcg_gen_and_vec',
'tcg_gen_andc_i32',
'tcg_gen_andc_i64',
'tcg_gen_andc_vec',
'tcg_gen_andi_i32',
'tcg_gen_andi_i64',
'tcg_gen_atomic_add_fetch_i32',
@ -3057,6 +3064,12 @@ symbols = (
'tcg_gen_div_i64',
'tcg_gen_divu_i32',
'tcg_gen_divu_i64',
'tcg_gen_dup8i_vec',
'tcg_gen_dup16i_vec',
'tcg_gen_dup32i_vec',
'tcg_gen_dup64i_vec',
'tcg_gen_dup_i32_vec',
'tcg_gen_dup_i64_vec',
'tcg_gen_eqv_i32',
'tcg_gen_eqv_i64',
'tcg_gen_exit_tb',
@ -3088,12 +3101,14 @@ symbols = (
'tcg_gen_ld8u_i64',
'tcg_gen_ld_i32',
'tcg_gen_ld_i64',
'tcg_gen_ld_vec',
'tcg_gen_ldst_op_i32',
'tcg_gen_ldst_op_i64',
'tcg_gen_lookup_and_goto_ptr',
'tcg_gen_mb',
'tcg_gen_mov_i32',
'tcg_gen_mov_i64',
'tcg_gen_mov_vec',
'tcg_gen_movcond_i32',
'tcg_gen_movcond_i64',
'tcg_gen_movi_i32',
@ -3112,10 +3127,13 @@ symbols = (
'tcg_gen_nand_i64',
'tcg_gen_neg_i32',
'tcg_gen_neg_i64',
'tcg_gen_neg_vec',
'tcg_gen_nor_i32',
'tcg_gen_nor_i64',
'tcg_gen_nor_vec',
'tcg_gen_not_i32',
'tcg_gen_not_i64',
'tcg_gen_not_vec',
'tcg_gen_op1',
'tcg_gen_op1i',
'tcg_gen_op2',
@ -3139,8 +3157,10 @@ symbols = (
'tcg_gen_op6i_i64',
'tcg_gen_or_i32',
'tcg_gen_or_i64',
'tcg_gen_or_vec',
'tcg_gen_orc_i32',
'tcg_gen_orc_i64',
'tcg_gen_orc_vec',
'tcg_gen_ori_i32',
'tcg_gen_ori_i64',
'tcg_gen_qemu_ld_i32',
@ -3180,16 +3200,20 @@ symbols = (
'tcg_gen_shri_i64',
'tcg_gen_st_i32',
'tcg_gen_st_i64',
'tcg_gen_st_vec',
'tcg_gen_stl_vec',
'tcg_gen_sub2_i32',
'tcg_gen_sub2_i64',
'tcg_gen_sub_i32',
'tcg_gen_sub_i64',
'tcg_gen_sub_vec',
'tcg_gen_subfi_i32',
'tcg_gen_subfi_i64',
'tcg_gen_subi_i32',
'tcg_gen_subi_i64',
'tcg_gen_xor_i32',
'tcg_gen_xor_i64',
'tcg_gen_xor_vec',
'tcg_gen_xori_i32',
'tcg_gen_xori_i64',
'tcg_get_arg_str_i32',
@ -3296,6 +3320,7 @@ symbols = (
'tcg_temp_alloc',
'tcg_temp_free_i32',
'tcg_temp_free_i64',
'tcg_temp_free_vec',
'tcg_temp_free_internal',
'tcg_temp_local_new_i32',
'tcg_temp_local_new_i64',
@ -3304,6 +3329,8 @@ symbols = (
'tcg_temp_new_internal',
'tcg_temp_new_internal_i32',
'tcg_temp_new_internal_i64',
'tcg_temp_new_vec',
'tcg_temp_new_vec_matching',
'tdb_hash',
'teecr_write',
'teehbr_access',
@ -3401,6 +3428,9 @@ symbols = (
'v8_el3_no_el2_cp_reginfo',
'vapa_cp_reginfo',
'vbar_write',
'vec_gen_2',
'vec_gen_3',
'vec_gen_4',
'vfp_exceptbits_from_host',
'vfp_exceptbits_to_host',
'vfp_get_fpcr',

30
qemu/m68k.h
View file

@ -2971,6 +2971,10 @@
#define tcg_const_i64 tcg_const_i64_m68k
#define tcg_const_local_i32 tcg_const_local_i32_m68k
#define tcg_const_local_i64 tcg_const_local_i64_m68k
#define tcg_const_ones_vec tcg_const_ones_vec_m68k
#define tcg_const_ones_vec_matching tcg_const_ones_vec_matching_m68k
#define tcg_const_zeros_vec tcg_const_zeros_vec_m68k
#define tcg_const_zeros_vec_matching tcg_const_zeros_vec_matching_m68k
#define tcg_constant_folding tcg_constant_folding_m68k
#define tcg_context_init tcg_context_init_m68k
#define tcg_cpu_exec tcg_cpu_exec_m68k
@ -2989,12 +2993,15 @@
#define tcg_gen_add2_i64 tcg_gen_add2_i64_m68k
#define tcg_gen_add_i32 tcg_gen_add_i32_m68k
#define tcg_gen_add_i64 tcg_gen_add_i64_m68k
#define tcg_gen_add_vec tcg_gen_add_vec_m68k
#define tcg_gen_addi_i32 tcg_gen_addi_i32_m68k
#define tcg_gen_addi_i64 tcg_gen_addi_i64_m68k
#define tcg_gen_and_i32 tcg_gen_and_i32_m68k
#define tcg_gen_and_i64 tcg_gen_and_i64_m68k
#define tcg_gen_and_vec tcg_gen_and_vec_m68k
#define tcg_gen_andc_i32 tcg_gen_andc_i32_m68k
#define tcg_gen_andc_i64 tcg_gen_andc_i64_m68k
#define tcg_gen_andc_vec tcg_gen_andc_vec_m68k
#define tcg_gen_andi_i32 tcg_gen_andi_i32_m68k
#define tcg_gen_andi_i64 tcg_gen_andi_i64_m68k
#define tcg_gen_atomic_add_fetch_i32 tcg_gen_atomic_add_fetch_i32_m68k
@ -3051,6 +3058,12 @@
#define tcg_gen_div_i64 tcg_gen_div_i64_m68k
#define tcg_gen_divu_i32 tcg_gen_divu_i32_m68k
#define tcg_gen_divu_i64 tcg_gen_divu_i64_m68k
#define tcg_gen_dup8i_vec tcg_gen_dup8i_vec_m68k
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_m68k
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_m68k
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_m68k
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_m68k
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_m68k
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_m68k
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_m68k
#define tcg_gen_exit_tb tcg_gen_exit_tb_m68k
@ -3082,12 +3095,14 @@
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_m68k
#define tcg_gen_ld_i32 tcg_gen_ld_i32_m68k
#define tcg_gen_ld_i64 tcg_gen_ld_i64_m68k
#define tcg_gen_ld_vec tcg_gen_ld_vec_m68k
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_m68k
#define tcg_gen_ldst_op_i64 tcg_gen_ldst_op_i64_m68k
#define tcg_gen_lookup_and_goto_ptr tcg_gen_lookup_and_goto_ptr_m68k
#define tcg_gen_mb tcg_gen_mb_m68k
#define tcg_gen_mov_i32 tcg_gen_mov_i32_m68k
#define tcg_gen_mov_i64 tcg_gen_mov_i64_m68k
#define tcg_gen_mov_vec tcg_gen_mov_vec_m68k
#define tcg_gen_movcond_i32 tcg_gen_movcond_i32_m68k
#define tcg_gen_movcond_i64 tcg_gen_movcond_i64_m68k
#define tcg_gen_movi_i32 tcg_gen_movi_i32_m68k
@ -3106,10 +3121,13 @@
#define tcg_gen_nand_i64 tcg_gen_nand_i64_m68k
#define tcg_gen_neg_i32 tcg_gen_neg_i32_m68k
#define tcg_gen_neg_i64 tcg_gen_neg_i64_m68k
#define tcg_gen_neg_vec tcg_gen_neg_vec_m68k
#define tcg_gen_nor_i32 tcg_gen_nor_i32_m68k
#define tcg_gen_nor_i64 tcg_gen_nor_i64_m68k
#define tcg_gen_nor_vec tcg_gen_nor_vec_m68k
#define tcg_gen_not_i32 tcg_gen_not_i32_m68k
#define tcg_gen_not_i64 tcg_gen_not_i64_m68k
#define tcg_gen_not_vec tcg_gen_not_vec_m68k
#define tcg_gen_op1 tcg_gen_op1_m68k
#define tcg_gen_op1i tcg_gen_op1i_m68k
#define tcg_gen_op2 tcg_gen_op2_m68k
@ -3133,8 +3151,10 @@
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_m68k
#define tcg_gen_or_i32 tcg_gen_or_i32_m68k
#define tcg_gen_or_i64 tcg_gen_or_i64_m68k
#define tcg_gen_or_vec tcg_gen_or_vec_m68k
#define tcg_gen_orc_i32 tcg_gen_orc_i32_m68k
#define tcg_gen_orc_i64 tcg_gen_orc_i64_m68k
#define tcg_gen_orc_vec tcg_gen_orc_vec_m68k
#define tcg_gen_ori_i32 tcg_gen_ori_i32_m68k
#define tcg_gen_ori_i64 tcg_gen_ori_i64_m68k
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_m68k
@ -3174,16 +3194,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_m68k
#define tcg_gen_st_i32 tcg_gen_st_i32_m68k
#define tcg_gen_st_i64 tcg_gen_st_i64_m68k
#define tcg_gen_st_vec tcg_gen_st_vec_m68k
#define tcg_gen_stl_vec tcg_gen_stl_vec_m68k
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_m68k
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_m68k
#define tcg_gen_sub_i32 tcg_gen_sub_i32_m68k
#define tcg_gen_sub_i64 tcg_gen_sub_i64_m68k
#define tcg_gen_sub_vec tcg_gen_sub_vec_m68k
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_m68k
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_m68k
#define tcg_gen_subi_i32 tcg_gen_subi_i32_m68k
#define tcg_gen_subi_i64 tcg_gen_subi_i64_m68k
#define tcg_gen_xor_i32 tcg_gen_xor_i32_m68k
#define tcg_gen_xor_i64 tcg_gen_xor_i64_m68k
#define tcg_gen_xor_vec tcg_gen_xor_vec_m68k
#define tcg_gen_xori_i32 tcg_gen_xori_i32_m68k
#define tcg_gen_xori_i64 tcg_gen_xori_i64_m68k
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_m68k
@ -3290,6 +3314,7 @@
#define tcg_temp_alloc tcg_temp_alloc_m68k
#define tcg_temp_free_i32 tcg_temp_free_i32_m68k
#define tcg_temp_free_i64 tcg_temp_free_i64_m68k
#define tcg_temp_free_vec tcg_temp_free_vec_m68k
#define tcg_temp_free_internal tcg_temp_free_internal_m68k
#define tcg_temp_local_new_i32 tcg_temp_local_new_i32_m68k
#define tcg_temp_local_new_i64 tcg_temp_local_new_i64_m68k
@ -3298,6 +3323,8 @@
#define tcg_temp_new_internal tcg_temp_new_internal_m68k
#define tcg_temp_new_internal_i32 tcg_temp_new_internal_i32_m68k
#define tcg_temp_new_internal_i64 tcg_temp_new_internal_i64_m68k
#define tcg_temp_new_vec tcg_temp_new_vec_m68k
#define tcg_temp_new_vec_matching tcg_temp_new_vec_matching_m68k
#define tdb_hash tdb_hash_m68k
#define teecr_write teecr_write_m68k
#define teehbr_access teehbr_access_m68k
@ -3395,6 +3422,9 @@
#define v8_el3_no_el2_cp_reginfo v8_el3_no_el2_cp_reginfo_m68k
#define vapa_cp_reginfo vapa_cp_reginfo_m68k
#define vbar_write vbar_write_m68k
#define vec_gen_2 vec_gen_2_m68k
#define vec_gen_3 vec_gen_3_m68k
#define vec_gen_4 vec_gen_4_m68k
#define vfp_exceptbits_from_host vfp_exceptbits_from_host_m68k
#define vfp_exceptbits_to_host vfp_exceptbits_to_host_m68k
#define vfp_get_fpcr vfp_get_fpcr_m68k

30
qemu/mips.h
View file

@ -2971,6 +2971,10 @@
#define tcg_const_i64 tcg_const_i64_mips
#define tcg_const_local_i32 tcg_const_local_i32_mips
#define tcg_const_local_i64 tcg_const_local_i64_mips
#define tcg_const_ones_vec tcg_const_ones_vec_mips
#define tcg_const_ones_vec_matching tcg_const_ones_vec_matching_mips
#define tcg_const_zeros_vec tcg_const_zeros_vec_mips
#define tcg_const_zeros_vec_matching tcg_const_zeros_vec_matching_mips
#define tcg_constant_folding tcg_constant_folding_mips
#define tcg_context_init tcg_context_init_mips
#define tcg_cpu_exec tcg_cpu_exec_mips
@ -2989,12 +2993,15 @@
#define tcg_gen_add2_i64 tcg_gen_add2_i64_mips
#define tcg_gen_add_i32 tcg_gen_add_i32_mips
#define tcg_gen_add_i64 tcg_gen_add_i64_mips
#define tcg_gen_add_vec tcg_gen_add_vec_mips
#define tcg_gen_addi_i32 tcg_gen_addi_i32_mips
#define tcg_gen_addi_i64 tcg_gen_addi_i64_mips
#define tcg_gen_and_i32 tcg_gen_and_i32_mips
#define tcg_gen_and_i64 tcg_gen_and_i64_mips
#define tcg_gen_and_vec tcg_gen_and_vec_mips
#define tcg_gen_andc_i32 tcg_gen_andc_i32_mips
#define tcg_gen_andc_i64 tcg_gen_andc_i64_mips
#define tcg_gen_andc_vec tcg_gen_andc_vec_mips
#define tcg_gen_andi_i32 tcg_gen_andi_i32_mips
#define tcg_gen_andi_i64 tcg_gen_andi_i64_mips
#define tcg_gen_atomic_add_fetch_i32 tcg_gen_atomic_add_fetch_i32_mips
@ -3051,6 +3058,12 @@
#define tcg_gen_div_i64 tcg_gen_div_i64_mips
#define tcg_gen_divu_i32 tcg_gen_divu_i32_mips
#define tcg_gen_divu_i64 tcg_gen_divu_i64_mips
#define tcg_gen_dup8i_vec tcg_gen_dup8i_vec_mips
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_mips
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_mips
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_mips
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_mips
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_mips
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_mips
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_mips
#define tcg_gen_exit_tb tcg_gen_exit_tb_mips
@ -3082,12 +3095,14 @@
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_mips
#define tcg_gen_ld_i32 tcg_gen_ld_i32_mips
#define tcg_gen_ld_i64 tcg_gen_ld_i64_mips
#define tcg_gen_ld_vec tcg_gen_ld_vec_mips
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_mips
#define tcg_gen_ldst_op_i64 tcg_gen_ldst_op_i64_mips
#define tcg_gen_lookup_and_goto_ptr tcg_gen_lookup_and_goto_ptr_mips
#define tcg_gen_mb tcg_gen_mb_mips
#define tcg_gen_mov_i32 tcg_gen_mov_i32_mips
#define tcg_gen_mov_i64 tcg_gen_mov_i64_mips
#define tcg_gen_mov_vec tcg_gen_mov_vec_mips
#define tcg_gen_movcond_i32 tcg_gen_movcond_i32_mips
#define tcg_gen_movcond_i64 tcg_gen_movcond_i64_mips
#define tcg_gen_movi_i32 tcg_gen_movi_i32_mips
@ -3106,10 +3121,13 @@
#define tcg_gen_nand_i64 tcg_gen_nand_i64_mips
#define tcg_gen_neg_i32 tcg_gen_neg_i32_mips
#define tcg_gen_neg_i64 tcg_gen_neg_i64_mips
#define tcg_gen_neg_vec tcg_gen_neg_vec_mips
#define tcg_gen_nor_i32 tcg_gen_nor_i32_mips
#define tcg_gen_nor_i64 tcg_gen_nor_i64_mips
#define tcg_gen_nor_vec tcg_gen_nor_vec_mips
#define tcg_gen_not_i32 tcg_gen_not_i32_mips
#define tcg_gen_not_i64 tcg_gen_not_i64_mips
#define tcg_gen_not_vec tcg_gen_not_vec_mips
#define tcg_gen_op1 tcg_gen_op1_mips
#define tcg_gen_op1i tcg_gen_op1i_mips
#define tcg_gen_op2 tcg_gen_op2_mips
@ -3133,8 +3151,10 @@
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_mips
#define tcg_gen_or_i32 tcg_gen_or_i32_mips
#define tcg_gen_or_i64 tcg_gen_or_i64_mips
#define tcg_gen_or_vec tcg_gen_or_vec_mips
#define tcg_gen_orc_i32 tcg_gen_orc_i32_mips
#define tcg_gen_orc_i64 tcg_gen_orc_i64_mips
#define tcg_gen_orc_vec tcg_gen_orc_vec_mips
#define tcg_gen_ori_i32 tcg_gen_ori_i32_mips
#define tcg_gen_ori_i64 tcg_gen_ori_i64_mips
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_mips
@ -3174,16 +3194,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_mips
#define tcg_gen_st_i32 tcg_gen_st_i32_mips
#define tcg_gen_st_i64 tcg_gen_st_i64_mips
#define tcg_gen_st_vec tcg_gen_st_vec_mips
#define tcg_gen_stl_vec tcg_gen_stl_vec_mips
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_mips
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_mips
#define tcg_gen_sub_i32 tcg_gen_sub_i32_mips
#define tcg_gen_sub_i64 tcg_gen_sub_i64_mips
#define tcg_gen_sub_vec tcg_gen_sub_vec_mips
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_mips
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mips
#define tcg_gen_subi_i32 tcg_gen_subi_i32_mips
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mips
#define tcg_gen_xor_i32 tcg_gen_xor_i32_mips
#define tcg_gen_xor_i64 tcg_gen_xor_i64_mips
#define tcg_gen_xor_vec tcg_gen_xor_vec_mips
#define tcg_gen_xori_i32 tcg_gen_xori_i32_mips
#define tcg_gen_xori_i64 tcg_gen_xori_i64_mips
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_mips
@ -3290,6 +3314,7 @@
#define tcg_temp_alloc tcg_temp_alloc_mips
#define tcg_temp_free_i32 tcg_temp_free_i32_mips
#define tcg_temp_free_i64 tcg_temp_free_i64_mips
#define tcg_temp_free_vec tcg_temp_free_vec_mips
#define tcg_temp_free_internal tcg_temp_free_internal_mips
#define tcg_temp_local_new_i32 tcg_temp_local_new_i32_mips
#define tcg_temp_local_new_i64 tcg_temp_local_new_i64_mips
@ -3298,6 +3323,8 @@
#define tcg_temp_new_internal tcg_temp_new_internal_mips
#define tcg_temp_new_internal_i32 tcg_temp_new_internal_i32_mips
#define tcg_temp_new_internal_i64 tcg_temp_new_internal_i64_mips
#define tcg_temp_new_vec tcg_temp_new_vec_mips
#define tcg_temp_new_vec_matching tcg_temp_new_vec_matching_mips
#define tdb_hash tdb_hash_mips
#define teecr_write teecr_write_mips
#define teehbr_access teehbr_access_mips
@ -3395,6 +3422,9 @@
#define v8_el3_no_el2_cp_reginfo v8_el3_no_el2_cp_reginfo_mips
#define vapa_cp_reginfo vapa_cp_reginfo_mips
#define vbar_write vbar_write_mips
#define vec_gen_2 vec_gen_2_mips
#define vec_gen_3 vec_gen_3_mips
#define vec_gen_4 vec_gen_4_mips
#define vfp_exceptbits_from_host vfp_exceptbits_from_host_mips
#define vfp_exceptbits_to_host vfp_exceptbits_to_host_mips
#define vfp_get_fpcr vfp_get_fpcr_mips

30
qemu/mips64.h
View file

@ -2971,6 +2971,10 @@
#define tcg_const_i64 tcg_const_i64_mips64
#define tcg_const_local_i32 tcg_const_local_i32_mips64
#define tcg_const_local_i64 tcg_const_local_i64_mips64
#define tcg_const_ones_vec tcg_const_ones_vec_mips64
#define tcg_const_ones_vec_matching tcg_const_ones_vec_matching_mips64
#define tcg_const_zeros_vec tcg_const_zeros_vec_mips64
#define tcg_const_zeros_vec_matching tcg_const_zeros_vec_matching_mips64
#define tcg_constant_folding tcg_constant_folding_mips64
#define tcg_context_init tcg_context_init_mips64
#define tcg_cpu_exec tcg_cpu_exec_mips64
@ -2989,12 +2993,15 @@
#define tcg_gen_add2_i64 tcg_gen_add2_i64_mips64
#define tcg_gen_add_i32 tcg_gen_add_i32_mips64
#define tcg_gen_add_i64 tcg_gen_add_i64_mips64
#define tcg_gen_add_vec tcg_gen_add_vec_mips64
#define tcg_gen_addi_i32 tcg_gen_addi_i32_mips64
#define tcg_gen_addi_i64 tcg_gen_addi_i64_mips64
#define tcg_gen_and_i32 tcg_gen_and_i32_mips64
#define tcg_gen_and_i64 tcg_gen_and_i64_mips64
#define tcg_gen_and_vec tcg_gen_and_vec_mips64
#define tcg_gen_andc_i32 tcg_gen_andc_i32_mips64
#define tcg_gen_andc_i64 tcg_gen_andc_i64_mips64
#define tcg_gen_andc_vec tcg_gen_andc_vec_mips64
#define tcg_gen_andi_i32 tcg_gen_andi_i32_mips64
#define tcg_gen_andi_i64 tcg_gen_andi_i64_mips64
#define tcg_gen_atomic_add_fetch_i32 tcg_gen_atomic_add_fetch_i32_mips64
@ -3051,6 +3058,12 @@
#define tcg_gen_div_i64 tcg_gen_div_i64_mips64
#define tcg_gen_divu_i32 tcg_gen_divu_i32_mips64
#define tcg_gen_divu_i64 tcg_gen_divu_i64_mips64
#define tcg_gen_dup8i_vec tcg_gen_dup8i_vec_mips64
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_mips64
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_mips64
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_mips64
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_mips64
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_mips64
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_mips64
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_mips64
#define tcg_gen_exit_tb tcg_gen_exit_tb_mips64
@ -3082,12 +3095,14 @@
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_mips64
#define tcg_gen_ld_i32 tcg_gen_ld_i32_mips64
#define tcg_gen_ld_i64 tcg_gen_ld_i64_mips64
#define tcg_gen_ld_vec tcg_gen_ld_vec_mips64
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_mips64
#define tcg_gen_ldst_op_i64 tcg_gen_ldst_op_i64_mips64
#define tcg_gen_lookup_and_goto_ptr tcg_gen_lookup_and_goto_ptr_mips64
#define tcg_gen_mb tcg_gen_mb_mips64
#define tcg_gen_mov_i32 tcg_gen_mov_i32_mips64
#define tcg_gen_mov_i64 tcg_gen_mov_i64_mips64
#define tcg_gen_mov_vec tcg_gen_mov_vec_mips64
#define tcg_gen_movcond_i32 tcg_gen_movcond_i32_mips64
#define tcg_gen_movcond_i64 tcg_gen_movcond_i64_mips64
#define tcg_gen_movi_i32 tcg_gen_movi_i32_mips64
@ -3106,10 +3121,13 @@
#define tcg_gen_nand_i64 tcg_gen_nand_i64_mips64
#define tcg_gen_neg_i32 tcg_gen_neg_i32_mips64
#define tcg_gen_neg_i64 tcg_gen_neg_i64_mips64
#define tcg_gen_neg_vec tcg_gen_neg_vec_mips64
#define tcg_gen_nor_i32 tcg_gen_nor_i32_mips64
#define tcg_gen_nor_i64 tcg_gen_nor_i64_mips64
#define tcg_gen_nor_vec tcg_gen_nor_vec_mips64
#define tcg_gen_not_i32 tcg_gen_not_i32_mips64
#define tcg_gen_not_i64 tcg_gen_not_i64_mips64
#define tcg_gen_not_vec tcg_gen_not_vec_mips64
#define tcg_gen_op1 tcg_gen_op1_mips64
#define tcg_gen_op1i tcg_gen_op1i_mips64
#define tcg_gen_op2 tcg_gen_op2_mips64
@ -3133,8 +3151,10 @@
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_mips64
#define tcg_gen_or_i32 tcg_gen_or_i32_mips64
#define tcg_gen_or_i64 tcg_gen_or_i64_mips64
#define tcg_gen_or_vec tcg_gen_or_vec_mips64
#define tcg_gen_orc_i32 tcg_gen_orc_i32_mips64
#define tcg_gen_orc_i64 tcg_gen_orc_i64_mips64
#define tcg_gen_orc_vec tcg_gen_orc_vec_mips64
#define tcg_gen_ori_i32 tcg_gen_ori_i32_mips64
#define tcg_gen_ori_i64 tcg_gen_ori_i64_mips64
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_mips64
@ -3174,16 +3194,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_mips64
#define tcg_gen_st_i32 tcg_gen_st_i32_mips64
#define tcg_gen_st_i64 tcg_gen_st_i64_mips64
#define tcg_gen_st_vec tcg_gen_st_vec_mips64
#define tcg_gen_stl_vec tcg_gen_stl_vec_mips64
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_mips64
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_mips64
#define tcg_gen_sub_i32 tcg_gen_sub_i32_mips64
#define tcg_gen_sub_i64 tcg_gen_sub_i64_mips64
#define tcg_gen_sub_vec tcg_gen_sub_vec_mips64
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_mips64
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mips64
#define tcg_gen_subi_i32 tcg_gen_subi_i32_mips64
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mips64
#define tcg_gen_xor_i32 tcg_gen_xor_i32_mips64
#define tcg_gen_xor_i64 tcg_gen_xor_i64_mips64
#define tcg_gen_xor_vec tcg_gen_xor_vec_mips64
#define tcg_gen_xori_i32 tcg_gen_xori_i32_mips64
#define tcg_gen_xori_i64 tcg_gen_xori_i64_mips64
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_mips64
@ -3290,6 +3314,7 @@
#define tcg_temp_alloc tcg_temp_alloc_mips64
#define tcg_temp_free_i32 tcg_temp_free_i32_mips64
#define tcg_temp_free_i64 tcg_temp_free_i64_mips64
#define tcg_temp_free_vec tcg_temp_free_vec_mips64
#define tcg_temp_free_internal tcg_temp_free_internal_mips64
#define tcg_temp_local_new_i32 tcg_temp_local_new_i32_mips64
#define tcg_temp_local_new_i64 tcg_temp_local_new_i64_mips64
@ -3298,6 +3323,8 @@
#define tcg_temp_new_internal tcg_temp_new_internal_mips64
#define tcg_temp_new_internal_i32 tcg_temp_new_internal_i32_mips64
#define tcg_temp_new_internal_i64 tcg_temp_new_internal_i64_mips64
#define tcg_temp_new_vec tcg_temp_new_vec_mips64
#define tcg_temp_new_vec_matching tcg_temp_new_vec_matching_mips64
#define tdb_hash tdb_hash_mips64
#define teecr_write teecr_write_mips64
#define teehbr_access teehbr_access_mips64
@ -3395,6 +3422,9 @@
#define v8_el3_no_el2_cp_reginfo v8_el3_no_el2_cp_reginfo_mips64
#define vapa_cp_reginfo vapa_cp_reginfo_mips64
#define vbar_write vbar_write_mips64
#define vec_gen_2 vec_gen_2_mips64
#define vec_gen_3 vec_gen_3_mips64
#define vec_gen_4 vec_gen_4_mips64
#define vfp_exceptbits_from_host vfp_exceptbits_from_host_mips64
#define vfp_exceptbits_to_host vfp_exceptbits_to_host_mips64
#define vfp_get_fpcr vfp_get_fpcr_mips64

30
qemu/mips64el.h
View file

@ -2971,6 +2971,10 @@
#define tcg_const_i64 tcg_const_i64_mips64el
#define tcg_const_local_i32 tcg_const_local_i32_mips64el
#define tcg_const_local_i64 tcg_const_local_i64_mips64el
#define tcg_const_ones_vec tcg_const_ones_vec_mips64el
#define tcg_const_ones_vec_matching tcg_const_ones_vec_matching_mips64el
#define tcg_const_zeros_vec tcg_const_zeros_vec_mips64el
#define tcg_const_zeros_vec_matching tcg_const_zeros_vec_matching_mips64el
#define tcg_constant_folding tcg_constant_folding_mips64el
#define tcg_context_init tcg_context_init_mips64el
#define tcg_cpu_exec tcg_cpu_exec_mips64el
@ -2989,12 +2993,15 @@
#define tcg_gen_add2_i64 tcg_gen_add2_i64_mips64el
#define tcg_gen_add_i32 tcg_gen_add_i32_mips64el
#define tcg_gen_add_i64 tcg_gen_add_i64_mips64el
#define tcg_gen_add_vec tcg_gen_add_vec_mips64el
#define tcg_gen_addi_i32 tcg_gen_addi_i32_mips64el
#define tcg_gen_addi_i64 tcg_gen_addi_i64_mips64el
#define tcg_gen_and_i32 tcg_gen_and_i32_mips64el
#define tcg_gen_and_i64 tcg_gen_and_i64_mips64el
#define tcg_gen_and_vec tcg_gen_and_vec_mips64el
#define tcg_gen_andc_i32 tcg_gen_andc_i32_mips64el
#define tcg_gen_andc_i64 tcg_gen_andc_i64_mips64el
#define tcg_gen_andc_vec tcg_gen_andc_vec_mips64el
#define tcg_gen_andi_i32 tcg_gen_andi_i32_mips64el
#define tcg_gen_andi_i64 tcg_gen_andi_i64_mips64el
#define tcg_gen_atomic_add_fetch_i32 tcg_gen_atomic_add_fetch_i32_mips64el
@ -3051,6 +3058,12 @@
#define tcg_gen_div_i64 tcg_gen_div_i64_mips64el
#define tcg_gen_divu_i32 tcg_gen_divu_i32_mips64el
#define tcg_gen_divu_i64 tcg_gen_divu_i64_mips64el
#define tcg_gen_dup8i_vec tcg_gen_dup8i_vec_mips64el
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_mips64el
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_mips64el
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_mips64el
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_mips64el
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_mips64el
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_mips64el
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_mips64el
#define tcg_gen_exit_tb tcg_gen_exit_tb_mips64el
@ -3082,12 +3095,14 @@
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_mips64el
#define tcg_gen_ld_i32 tcg_gen_ld_i32_mips64el
#define tcg_gen_ld_i64 tcg_gen_ld_i64_mips64el
#define tcg_gen_ld_vec tcg_gen_ld_vec_mips64el
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_mips64el
#define tcg_gen_ldst_op_i64 tcg_gen_ldst_op_i64_mips64el
#define tcg_gen_lookup_and_goto_ptr tcg_gen_lookup_and_goto_ptr_mips64el
#define tcg_gen_mb tcg_gen_mb_mips64el
#define tcg_gen_mov_i32 tcg_gen_mov_i32_mips64el
#define tcg_gen_mov_i64 tcg_gen_mov_i64_mips64el
#define tcg_gen_mov_vec tcg_gen_mov_vec_mips64el
#define tcg_gen_movcond_i32 tcg_gen_movcond_i32_mips64el
#define tcg_gen_movcond_i64 tcg_gen_movcond_i64_mips64el
#define tcg_gen_movi_i32 tcg_gen_movi_i32_mips64el
@ -3106,10 +3121,13 @@
#define tcg_gen_nand_i64 tcg_gen_nand_i64_mips64el
#define tcg_gen_neg_i32 tcg_gen_neg_i32_mips64el
#define tcg_gen_neg_i64 tcg_gen_neg_i64_mips64el
#define tcg_gen_neg_vec tcg_gen_neg_vec_mips64el
#define tcg_gen_nor_i32 tcg_gen_nor_i32_mips64el
#define tcg_gen_nor_i64 tcg_gen_nor_i64_mips64el
#define tcg_gen_nor_vec tcg_gen_nor_vec_mips64el
#define tcg_gen_not_i32 tcg_gen_not_i32_mips64el
#define tcg_gen_not_i64 tcg_gen_not_i64_mips64el
#define tcg_gen_not_vec tcg_gen_not_vec_mips64el
#define tcg_gen_op1 tcg_gen_op1_mips64el
#define tcg_gen_op1i tcg_gen_op1i_mips64el
#define tcg_gen_op2 tcg_gen_op2_mips64el
@ -3133,8 +3151,10 @@
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_mips64el
#define tcg_gen_or_i32 tcg_gen_or_i32_mips64el
#define tcg_gen_or_i64 tcg_gen_or_i64_mips64el
#define tcg_gen_or_vec tcg_gen_or_vec_mips64el
#define tcg_gen_orc_i32 tcg_gen_orc_i32_mips64el
#define tcg_gen_orc_i64 tcg_gen_orc_i64_mips64el
#define tcg_gen_orc_vec tcg_gen_orc_vec_mips64el
#define tcg_gen_ori_i32 tcg_gen_ori_i32_mips64el
#define tcg_gen_ori_i64 tcg_gen_ori_i64_mips64el
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_mips64el
@ -3174,16 +3194,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_mips64el
#define tcg_gen_st_i32 tcg_gen_st_i32_mips64el
#define tcg_gen_st_i64 tcg_gen_st_i64_mips64el
#define tcg_gen_st_vec tcg_gen_st_vec_mips64el
#define tcg_gen_stl_vec tcg_gen_stl_vec_mips64el
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_mips64el
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_mips64el
#define tcg_gen_sub_i32 tcg_gen_sub_i32_mips64el
#define tcg_gen_sub_i64 tcg_gen_sub_i64_mips64el
#define tcg_gen_sub_vec tcg_gen_sub_vec_mips64el
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_mips64el
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mips64el
#define tcg_gen_subi_i32 tcg_gen_subi_i32_mips64el
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mips64el
#define tcg_gen_xor_i32 tcg_gen_xor_i32_mips64el
#define tcg_gen_xor_i64 tcg_gen_xor_i64_mips64el
#define tcg_gen_xor_vec tcg_gen_xor_vec_mips64el
#define tcg_gen_xori_i32 tcg_gen_xori_i32_mips64el
#define tcg_gen_xori_i64 tcg_gen_xori_i64_mips64el
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_mips64el
@ -3290,6 +3314,7 @@
#define tcg_temp_alloc tcg_temp_alloc_mips64el
#define tcg_temp_free_i32 tcg_temp_free_i32_mips64el
#define tcg_temp_free_i64 tcg_temp_free_i64_mips64el
#define tcg_temp_free_vec tcg_temp_free_vec_mips64el
#define tcg_temp_free_internal tcg_temp_free_internal_mips64el
#define tcg_temp_local_new_i32 tcg_temp_local_new_i32_mips64el
#define tcg_temp_local_new_i64 tcg_temp_local_new_i64_mips64el
@ -3298,6 +3323,8 @@
#define tcg_temp_new_internal tcg_temp_new_internal_mips64el
#define tcg_temp_new_internal_i32 tcg_temp_new_internal_i32_mips64el
#define tcg_temp_new_internal_i64 tcg_temp_new_internal_i64_mips64el
#define tcg_temp_new_vec tcg_temp_new_vec_mips64el
#define tcg_temp_new_vec_matching tcg_temp_new_vec_matching_mips64el
#define tdb_hash tdb_hash_mips64el
#define teecr_write teecr_write_mips64el
#define teehbr_access teehbr_access_mips64el
@ -3395,6 +3422,9 @@
#define v8_el3_no_el2_cp_reginfo v8_el3_no_el2_cp_reginfo_mips64el
#define vapa_cp_reginfo vapa_cp_reginfo_mips64el
#define vbar_write vbar_write_mips64el
#define vec_gen_2 vec_gen_2_mips64el
#define vec_gen_3 vec_gen_3_mips64el
#define vec_gen_4 vec_gen_4_mips64el
#define vfp_exceptbits_from_host vfp_exceptbits_from_host_mips64el
#define vfp_exceptbits_to_host vfp_exceptbits_to_host_mips64el
#define vfp_get_fpcr vfp_get_fpcr_mips64el

30
qemu/mipsel.h
View file

@ -2971,6 +2971,10 @@
#define tcg_const_i64 tcg_const_i64_mipsel
#define tcg_const_local_i32 tcg_const_local_i32_mipsel
#define tcg_const_local_i64 tcg_const_local_i64_mipsel
#define tcg_const_ones_vec tcg_const_ones_vec_mipsel
#define tcg_const_ones_vec_matching tcg_const_ones_vec_matching_mipsel
#define tcg_const_zeros_vec tcg_const_zeros_vec_mipsel
#define tcg_const_zeros_vec_matching tcg_const_zeros_vec_matching_mipsel
#define tcg_constant_folding tcg_constant_folding_mipsel
#define tcg_context_init tcg_context_init_mipsel
#define tcg_cpu_exec tcg_cpu_exec_mipsel
@ -2989,12 +2993,15 @@
#define tcg_gen_add2_i64 tcg_gen_add2_i64_mipsel
#define tcg_gen_add_i32 tcg_gen_add_i32_mipsel
#define tcg_gen_add_i64 tcg_gen_add_i64_mipsel
#define tcg_gen_add_vec tcg_gen_add_vec_mipsel
#define tcg_gen_addi_i32 tcg_gen_addi_i32_mipsel
#define tcg_gen_addi_i64 tcg_gen_addi_i64_mipsel
#define tcg_gen_and_i32 tcg_gen_and_i32_mipsel
#define tcg_gen_and_i64 tcg_gen_and_i64_mipsel
#define tcg_gen_and_vec tcg_gen_and_vec_mipsel
#define tcg_gen_andc_i32 tcg_gen_andc_i32_mipsel
#define tcg_gen_andc_i64 tcg_gen_andc_i64_mipsel
#define tcg_gen_andc_vec tcg_gen_andc_vec_mipsel
#define tcg_gen_andi_i32 tcg_gen_andi_i32_mipsel
#define tcg_gen_andi_i64 tcg_gen_andi_i64_mipsel
#define tcg_gen_atomic_add_fetch_i32 tcg_gen_atomic_add_fetch_i32_mipsel
@ -3051,6 +3058,12 @@
#define tcg_gen_div_i64 tcg_gen_div_i64_mipsel
#define tcg_gen_divu_i32 tcg_gen_divu_i32_mipsel
#define tcg_gen_divu_i64 tcg_gen_divu_i64_mipsel
#define tcg_gen_dup8i_vec tcg_gen_dup8i_vec_mipsel
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_mipsel
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_mipsel
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_mipsel
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_mipsel
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_mipsel
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_mipsel
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_mipsel
#define tcg_gen_exit_tb tcg_gen_exit_tb_mipsel
@ -3082,12 +3095,14 @@
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_mipsel
#define tcg_gen_ld_i32 tcg_gen_ld_i32_mipsel
#define tcg_gen_ld_i64 tcg_gen_ld_i64_mipsel
#define tcg_gen_ld_vec tcg_gen_ld_vec_mipsel
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_mipsel
#define tcg_gen_ldst_op_i64 tcg_gen_ldst_op_i64_mipsel
#define tcg_gen_lookup_and_goto_ptr tcg_gen_lookup_and_goto_ptr_mipsel
#define tcg_gen_mb tcg_gen_mb_mipsel
#define tcg_gen_mov_i32 tcg_gen_mov_i32_mipsel
#define tcg_gen_mov_i64 tcg_gen_mov_i64_mipsel
#define tcg_gen_mov_vec tcg_gen_mov_vec_mipsel
#define tcg_gen_movcond_i32 tcg_gen_movcond_i32_mipsel
#define tcg_gen_movcond_i64 tcg_gen_movcond_i64_mipsel
#define tcg_gen_movi_i32 tcg_gen_movi_i32_mipsel
@ -3106,10 +3121,13 @@
#define tcg_gen_nand_i64 tcg_gen_nand_i64_mipsel
#define tcg_gen_neg_i32 tcg_gen_neg_i32_mipsel
#define tcg_gen_neg_i64 tcg_gen_neg_i64_mipsel
#define tcg_gen_neg_vec tcg_gen_neg_vec_mipsel
#define tcg_gen_nor_i32 tcg_gen_nor_i32_mipsel
#define tcg_gen_nor_i64 tcg_gen_nor_i64_mipsel
#define tcg_gen_nor_vec tcg_gen_nor_vec_mipsel
#define tcg_gen_not_i32 tcg_gen_not_i32_mipsel
#define tcg_gen_not_i64 tcg_gen_not_i64_mipsel
#define tcg_gen_not_vec tcg_gen_not_vec_mipsel
#define tcg_gen_op1 tcg_gen_op1_mipsel
#define tcg_gen_op1i tcg_gen_op1i_mipsel
#define tcg_gen_op2 tcg_gen_op2_mipsel
@ -3133,8 +3151,10 @@
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_mipsel
#define tcg_gen_or_i32 tcg_gen_or_i32_mipsel
#define tcg_gen_or_i64 tcg_gen_or_i64_mipsel
#define tcg_gen_or_vec tcg_gen_or_vec_mipsel
#define tcg_gen_orc_i32 tcg_gen_orc_i32_mipsel
#define tcg_gen_orc_i64 tcg_gen_orc_i64_mipsel
#define tcg_gen_orc_vec tcg_gen_orc_vec_mipsel
#define tcg_gen_ori_i32 tcg_gen_ori_i32_mipsel
#define tcg_gen_ori_i64 tcg_gen_ori_i64_mipsel
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_mipsel
@ -3174,16 +3194,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_mipsel
#define tcg_gen_st_i32 tcg_gen_st_i32_mipsel
#define tcg_gen_st_i64 tcg_gen_st_i64_mipsel
#define tcg_gen_st_vec tcg_gen_st_vec_mipsel
#define tcg_gen_stl_vec tcg_gen_stl_vec_mipsel
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_mipsel
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_mipsel
#define tcg_gen_sub_i32 tcg_gen_sub_i32_mipsel
#define tcg_gen_sub_i64 tcg_gen_sub_i64_mipsel
#define tcg_gen_sub_vec tcg_gen_sub_vec_mipsel
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_mipsel
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mipsel
#define tcg_gen_subi_i32 tcg_gen_subi_i32_mipsel
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mipsel
#define tcg_gen_xor_i32 tcg_gen_xor_i32_mipsel
#define tcg_gen_xor_i64 tcg_gen_xor_i64_mipsel
#define tcg_gen_xor_vec tcg_gen_xor_vec_mipsel
#define tcg_gen_xori_i32 tcg_gen_xori_i32_mipsel
#define tcg_gen_xori_i64 tcg_gen_xori_i64_mipsel
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_mipsel
@ -3290,6 +3314,7 @@
#define tcg_temp_alloc tcg_temp_alloc_mipsel
#define tcg_temp_free_i32 tcg_temp_free_i32_mipsel
#define tcg_temp_free_i64 tcg_temp_free_i64_mipsel
#define tcg_temp_free_vec tcg_temp_free_vec_mipsel
#define tcg_temp_free_internal tcg_temp_free_internal_mipsel
#define tcg_temp_local_new_i32 tcg_temp_local_new_i32_mipsel
#define tcg_temp_local_new_i64 tcg_temp_local_new_i64_mipsel
@ -3298,6 +3323,8 @@
#define tcg_temp_new_internal tcg_temp_new_internal_mipsel
#define tcg_temp_new_internal_i32 tcg_temp_new_internal_i32_mipsel
#define tcg_temp_new_internal_i64 tcg_temp_new_internal_i64_mipsel
#define tcg_temp_new_vec tcg_temp_new_vec_mipsel
#define tcg_temp_new_vec_matching tcg_temp_new_vec_matching_mipsel
#define tdb_hash tdb_hash_mipsel
#define teecr_write teecr_write_mipsel
#define teehbr_access teehbr_access_mipsel
@ -3395,6 +3422,9 @@
#define v8_el3_no_el2_cp_reginfo v8_el3_no_el2_cp_reginfo_mipsel
#define vapa_cp_reginfo vapa_cp_reginfo_mipsel
#define vbar_write vbar_write_mipsel
#define vec_gen_2 vec_gen_2_mipsel
#define vec_gen_3 vec_gen_3_mipsel
#define vec_gen_4 vec_gen_4_mipsel
#define vfp_exceptbits_from_host vfp_exceptbits_from_host_mipsel
#define vfp_exceptbits_to_host vfp_exceptbits_to_host_mipsel
#define vfp_get_fpcr vfp_get_fpcr_mipsel

30
qemu/powerpc.h
View file

@ -2971,6 +2971,10 @@
#define tcg_const_i64 tcg_const_i64_powerpc
#define tcg_const_local_i32 tcg_const_local_i32_powerpc
#define tcg_const_local_i64 tcg_const_local_i64_powerpc
#define tcg_const_ones_vec tcg_const_ones_vec_powerpc
#define tcg_const_ones_vec_matching tcg_const_ones_vec_matching_powerpc
#define tcg_const_zeros_vec tcg_const_zeros_vec_powerpc
#define tcg_const_zeros_vec_matching tcg_const_zeros_vec_matching_powerpc
#define tcg_constant_folding tcg_constant_folding_powerpc
#define tcg_context_init tcg_context_init_powerpc
#define tcg_cpu_exec tcg_cpu_exec_powerpc
@ -2989,12 +2993,15 @@
#define tcg_gen_add2_i64 tcg_gen_add2_i64_powerpc
#define tcg_gen_add_i32 tcg_gen_add_i32_powerpc
#define tcg_gen_add_i64 tcg_gen_add_i64_powerpc
#define tcg_gen_add_vec tcg_gen_add_vec_powerpc
#define tcg_gen_addi_i32 tcg_gen_addi_i32_powerpc
#define tcg_gen_addi_i64 tcg_gen_addi_i64_powerpc
#define tcg_gen_and_i32 tcg_gen_and_i32_powerpc
#define tcg_gen_and_i64 tcg_gen_and_i64_powerpc
#define tcg_gen_and_vec tcg_gen_and_vec_powerpc
#define tcg_gen_andc_i32 tcg_gen_andc_i32_powerpc
#define tcg_gen_andc_i64 tcg_gen_andc_i64_powerpc
#define tcg_gen_andc_vec tcg_gen_andc_vec_powerpc
#define tcg_gen_andi_i32 tcg_gen_andi_i32_powerpc
#define tcg_gen_andi_i64 tcg_gen_andi_i64_powerpc
#define tcg_gen_atomic_add_fetch_i32 tcg_gen_atomic_add_fetch_i32_powerpc
@ -3051,6 +3058,12 @@
#define tcg_gen_div_i64 tcg_gen_div_i64_powerpc
#define tcg_gen_divu_i32 tcg_gen_divu_i32_powerpc
#define tcg_gen_divu_i64 tcg_gen_divu_i64_powerpc
#define tcg_gen_dup8i_vec tcg_gen_dup8i_vec_powerpc
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_powerpc
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_powerpc
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_powerpc
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_powerpc
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_powerpc
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_powerpc
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_powerpc
#define tcg_gen_exit_tb tcg_gen_exit_tb_powerpc
@ -3082,12 +3095,14 @@
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_powerpc
#define tcg_gen_ld_i32 tcg_gen_ld_i32_powerpc
#define tcg_gen_ld_i64 tcg_gen_ld_i64_powerpc
#define tcg_gen_ld_vec tcg_gen_ld_vec_powerpc
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_powerpc
#define tcg_gen_ldst_op_i64 tcg_gen_ldst_op_i64_powerpc
#define tcg_gen_lookup_and_goto_ptr tcg_gen_lookup_and_goto_ptr_powerpc
#define tcg_gen_mb tcg_gen_mb_powerpc
#define tcg_gen_mov_i32 tcg_gen_mov_i32_powerpc
#define tcg_gen_mov_i64 tcg_gen_mov_i64_powerpc
#define tcg_gen_mov_vec tcg_gen_mov_vec_powerpc
#define tcg_gen_movcond_i32 tcg_gen_movcond_i32_powerpc
#define tcg_gen_movcond_i64 tcg_gen_movcond_i64_powerpc
#define tcg_gen_movi_i32 tcg_gen_movi_i32_powerpc
@ -3106,10 +3121,13 @@
#define tcg_gen_nand_i64 tcg_gen_nand_i64_powerpc
#define tcg_gen_neg_i32 tcg_gen_neg_i32_powerpc
#define tcg_gen_neg_i64 tcg_gen_neg_i64_powerpc
#define tcg_gen_neg_vec tcg_gen_neg_vec_powerpc
#define tcg_gen_nor_i32 tcg_gen_nor_i32_powerpc
#define tcg_gen_nor_i64 tcg_gen_nor_i64_powerpc
#define tcg_gen_nor_vec tcg_gen_nor_vec_powerpc
#define tcg_gen_not_i32 tcg_gen_not_i32_powerpc
#define tcg_gen_not_i64 tcg_gen_not_i64_powerpc
#define tcg_gen_not_vec tcg_gen_not_vec_powerpc
#define tcg_gen_op1 tcg_gen_op1_powerpc
#define tcg_gen_op1i tcg_gen_op1i_powerpc
#define tcg_gen_op2 tcg_gen_op2_powerpc
@ -3133,8 +3151,10 @@
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_powerpc
#define tcg_gen_or_i32 tcg_gen_or_i32_powerpc
#define tcg_gen_or_i64 tcg_gen_or_i64_powerpc
#define tcg_gen_or_vec tcg_gen_or_vec_powerpc
#define tcg_gen_orc_i32 tcg_gen_orc_i32_powerpc
#define tcg_gen_orc_i64 tcg_gen_orc_i64_powerpc
#define tcg_gen_orc_vec tcg_gen_orc_vec_powerpc
#define tcg_gen_ori_i32 tcg_gen_ori_i32_powerpc
#define tcg_gen_ori_i64 tcg_gen_ori_i64_powerpc
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_powerpc
@ -3174,16 +3194,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_powerpc
#define tcg_gen_st_i32 tcg_gen_st_i32_powerpc
#define tcg_gen_st_i64 tcg_gen_st_i64_powerpc
#define tcg_gen_st_vec tcg_gen_st_vec_powerpc
#define tcg_gen_stl_vec tcg_gen_stl_vec_powerpc
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_powerpc
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_powerpc
#define tcg_gen_sub_i32 tcg_gen_sub_i32_powerpc
#define tcg_gen_sub_i64 tcg_gen_sub_i64_powerpc
#define tcg_gen_sub_vec tcg_gen_sub_vec_powerpc
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_powerpc
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_powerpc
#define tcg_gen_subi_i32 tcg_gen_subi_i32_powerpc
#define tcg_gen_subi_i64 tcg_gen_subi_i64_powerpc
#define tcg_gen_xor_i32 tcg_gen_xor_i32_powerpc
#define tcg_gen_xor_i64 tcg_gen_xor_i64_powerpc
#define tcg_gen_xor_vec tcg_gen_xor_vec_powerpc
#define tcg_gen_xori_i32 tcg_gen_xori_i32_powerpc
#define tcg_gen_xori_i64 tcg_gen_xori_i64_powerpc
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_powerpc
@ -3290,6 +3314,7 @@
#define tcg_temp_alloc tcg_temp_alloc_powerpc
#define tcg_temp_free_i32 tcg_temp_free_i32_powerpc
#define tcg_temp_free_i64 tcg_temp_free_i64_powerpc
#define tcg_temp_free_vec tcg_temp_free_vec_powerpc
#define tcg_temp_free_internal tcg_temp_free_internal_powerpc
#define tcg_temp_local_new_i32 tcg_temp_local_new_i32_powerpc
#define tcg_temp_local_new_i64 tcg_temp_local_new_i64_powerpc
@ -3298,6 +3323,8 @@
#define tcg_temp_new_internal tcg_temp_new_internal_powerpc
#define tcg_temp_new_internal_i32 tcg_temp_new_internal_i32_powerpc
#define tcg_temp_new_internal_i64 tcg_temp_new_internal_i64_powerpc
#define tcg_temp_new_vec tcg_temp_new_vec_powerpc
#define tcg_temp_new_vec_matching tcg_temp_new_vec_matching_powerpc
#define tdb_hash tdb_hash_powerpc
#define teecr_write teecr_write_powerpc
#define teehbr_access teehbr_access_powerpc
@ -3395,6 +3422,9 @@
#define v8_el3_no_el2_cp_reginfo v8_el3_no_el2_cp_reginfo_powerpc
#define vapa_cp_reginfo vapa_cp_reginfo_powerpc
#define vbar_write vbar_write_powerpc
#define vec_gen_2 vec_gen_2_powerpc
#define vec_gen_3 vec_gen_3_powerpc
#define vec_gen_4 vec_gen_4_powerpc
#define vfp_exceptbits_from_host vfp_exceptbits_from_host_powerpc
#define vfp_exceptbits_to_host vfp_exceptbits_to_host_powerpc
#define vfp_get_fpcr vfp_get_fpcr_powerpc

30
qemu/sparc.h
View file

@ -2971,6 +2971,10 @@
#define tcg_const_i64 tcg_const_i64_sparc
#define tcg_const_local_i32 tcg_const_local_i32_sparc
#define tcg_const_local_i64 tcg_const_local_i64_sparc
#define tcg_const_ones_vec tcg_const_ones_vec_sparc
#define tcg_const_ones_vec_matching tcg_const_ones_vec_matching_sparc
#define tcg_const_zeros_vec tcg_const_zeros_vec_sparc
#define tcg_const_zeros_vec_matching tcg_const_zeros_vec_matching_sparc
#define tcg_constant_folding tcg_constant_folding_sparc
#define tcg_context_init tcg_context_init_sparc
#define tcg_cpu_exec tcg_cpu_exec_sparc
@ -2989,12 +2993,15 @@
#define tcg_gen_add2_i64 tcg_gen_add2_i64_sparc
#define tcg_gen_add_i32 tcg_gen_add_i32_sparc
#define tcg_gen_add_i64 tcg_gen_add_i64_sparc
#define tcg_gen_add_vec tcg_gen_add_vec_sparc
#define tcg_gen_addi_i32 tcg_gen_addi_i32_sparc
#define tcg_gen_addi_i64 tcg_gen_addi_i64_sparc
#define tcg_gen_and_i32 tcg_gen_and_i32_sparc
#define tcg_gen_and_i64 tcg_gen_and_i64_sparc
#define tcg_gen_and_vec tcg_gen_and_vec_sparc
#define tcg_gen_andc_i32 tcg_gen_andc_i32_sparc
#define tcg_gen_andc_i64 tcg_gen_andc_i64_sparc
#define tcg_gen_andc_vec tcg_gen_andc_vec_sparc
#define tcg_gen_andi_i32 tcg_gen_andi_i32_sparc
#define tcg_gen_andi_i64 tcg_gen_andi_i64_sparc
#define tcg_gen_atomic_add_fetch_i32 tcg_gen_atomic_add_fetch_i32_sparc
@ -3051,6 +3058,12 @@
#define tcg_gen_div_i64 tcg_gen_div_i64_sparc
#define tcg_gen_divu_i32 tcg_gen_divu_i32_sparc
#define tcg_gen_divu_i64 tcg_gen_divu_i64_sparc
#define tcg_gen_dup8i_vec tcg_gen_dup8i_vec_sparc
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_sparc
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_sparc
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_sparc
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_sparc
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_sparc
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_sparc
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_sparc
#define tcg_gen_exit_tb tcg_gen_exit_tb_sparc
@ -3082,12 +3095,14 @@
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_sparc
#define tcg_gen_ld_i32 tcg_gen_ld_i32_sparc
#define tcg_gen_ld_i64 tcg_gen_ld_i64_sparc
#define tcg_gen_ld_vec tcg_gen_ld_vec_sparc
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_sparc
#define tcg_gen_ldst_op_i64 tcg_gen_ldst_op_i64_sparc
#define tcg_gen_lookup_and_goto_ptr tcg_gen_lookup_and_goto_ptr_sparc
#define tcg_gen_mb tcg_gen_mb_sparc
#define tcg_gen_mov_i32 tcg_gen_mov_i32_sparc
#define tcg_gen_mov_i64 tcg_gen_mov_i64_sparc
#define tcg_gen_mov_vec tcg_gen_mov_vec_sparc
#define tcg_gen_movcond_i32 tcg_gen_movcond_i32_sparc
#define tcg_gen_movcond_i64 tcg_gen_movcond_i64_sparc
#define tcg_gen_movi_i32 tcg_gen_movi_i32_sparc
@ -3106,10 +3121,13 @@
#define tcg_gen_nand_i64 tcg_gen_nand_i64_sparc
#define tcg_gen_neg_i32 tcg_gen_neg_i32_sparc
#define tcg_gen_neg_i64 tcg_gen_neg_i64_sparc
#define tcg_gen_neg_vec tcg_gen_neg_vec_sparc
#define tcg_gen_nor_i32 tcg_gen_nor_i32_sparc
#define tcg_gen_nor_i64 tcg_gen_nor_i64_sparc
#define tcg_gen_nor_vec tcg_gen_nor_vec_sparc
#define tcg_gen_not_i32 tcg_gen_not_i32_sparc
#define tcg_gen_not_i64 tcg_gen_not_i64_sparc
#define tcg_gen_not_vec tcg_gen_not_vec_sparc
#define tcg_gen_op1 tcg_gen_op1_sparc
#define tcg_gen_op1i tcg_gen_op1i_sparc
#define tcg_gen_op2 tcg_gen_op2_sparc
@ -3133,8 +3151,10 @@
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_sparc
#define tcg_gen_or_i32 tcg_gen_or_i32_sparc
#define tcg_gen_or_i64 tcg_gen_or_i64_sparc
#define tcg_gen_or_vec tcg_gen_or_vec_sparc
#define tcg_gen_orc_i32 tcg_gen_orc_i32_sparc
#define tcg_gen_orc_i64 tcg_gen_orc_i64_sparc
#define tcg_gen_orc_vec tcg_gen_orc_vec_sparc
#define tcg_gen_ori_i32 tcg_gen_ori_i32_sparc
#define tcg_gen_ori_i64 tcg_gen_ori_i64_sparc
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_sparc
@ -3174,16 +3194,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_sparc
#define tcg_gen_st_i32 tcg_gen_st_i32_sparc
#define tcg_gen_st_i64 tcg_gen_st_i64_sparc
#define tcg_gen_st_vec tcg_gen_st_vec_sparc
#define tcg_gen_stl_vec tcg_gen_stl_vec_sparc
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_sparc
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_sparc
#define tcg_gen_sub_i32 tcg_gen_sub_i32_sparc
#define tcg_gen_sub_i64 tcg_gen_sub_i64_sparc
#define tcg_gen_sub_vec tcg_gen_sub_vec_sparc
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_sparc
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_sparc
#define tcg_gen_subi_i32 tcg_gen_subi_i32_sparc
#define tcg_gen_subi_i64 tcg_gen_subi_i64_sparc
#define tcg_gen_xor_i32 tcg_gen_xor_i32_sparc
#define tcg_gen_xor_i64 tcg_gen_xor_i64_sparc
#define tcg_gen_xor_vec tcg_gen_xor_vec_sparc
#define tcg_gen_xori_i32 tcg_gen_xori_i32_sparc
#define tcg_gen_xori_i64 tcg_gen_xori_i64_sparc
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_sparc
@ -3290,6 +3314,7 @@
#define tcg_temp_alloc tcg_temp_alloc_sparc
#define tcg_temp_free_i32 tcg_temp_free_i32_sparc
#define tcg_temp_free_i64 tcg_temp_free_i64_sparc
#define tcg_temp_free_vec tcg_temp_free_vec_sparc
#define tcg_temp_free_internal tcg_temp_free_internal_sparc
#define tcg_temp_local_new_i32 tcg_temp_local_new_i32_sparc
#define tcg_temp_local_new_i64 tcg_temp_local_new_i64_sparc
@ -3298,6 +3323,8 @@
#define tcg_temp_new_internal tcg_temp_new_internal_sparc
#define tcg_temp_new_internal_i32 tcg_temp_new_internal_i32_sparc
#define tcg_temp_new_internal_i64 tcg_temp_new_internal_i64_sparc
#define tcg_temp_new_vec tcg_temp_new_vec_sparc
#define tcg_temp_new_vec_matching tcg_temp_new_vec_matching_sparc
#define tdb_hash tdb_hash_sparc
#define teecr_write teecr_write_sparc
#define teehbr_access teehbr_access_sparc
@ -3395,6 +3422,9 @@
#define v8_el3_no_el2_cp_reginfo v8_el3_no_el2_cp_reginfo_sparc
#define vapa_cp_reginfo vapa_cp_reginfo_sparc
#define vbar_write vbar_write_sparc
#define vec_gen_2 vec_gen_2_sparc
#define vec_gen_3 vec_gen_3_sparc
#define vec_gen_4 vec_gen_4_sparc
#define vfp_exceptbits_from_host vfp_exceptbits_from_host_sparc
#define vfp_exceptbits_to_host vfp_exceptbits_to_host_sparc
#define vfp_get_fpcr vfp_get_fpcr_sparc

30
qemu/sparc64.h
View file

@ -2971,6 +2971,10 @@
#define tcg_const_i64 tcg_const_i64_sparc64
#define tcg_const_local_i32 tcg_const_local_i32_sparc64
#define tcg_const_local_i64 tcg_const_local_i64_sparc64
#define tcg_const_ones_vec tcg_const_ones_vec_sparc64
#define tcg_const_ones_vec_matching tcg_const_ones_vec_matching_sparc64
#define tcg_const_zeros_vec tcg_const_zeros_vec_sparc64
#define tcg_const_zeros_vec_matching tcg_const_zeros_vec_matching_sparc64
#define tcg_constant_folding tcg_constant_folding_sparc64
#define tcg_context_init tcg_context_init_sparc64
#define tcg_cpu_exec tcg_cpu_exec_sparc64
@ -2989,12 +2993,15 @@
#define tcg_gen_add2_i64 tcg_gen_add2_i64_sparc64
#define tcg_gen_add_i32 tcg_gen_add_i32_sparc64
#define tcg_gen_add_i64 tcg_gen_add_i64_sparc64
#define tcg_gen_add_vec tcg_gen_add_vec_sparc64
#define tcg_gen_addi_i32 tcg_gen_addi_i32_sparc64
#define tcg_gen_addi_i64 tcg_gen_addi_i64_sparc64
#define tcg_gen_and_i32 tcg_gen_and_i32_sparc64
#define tcg_gen_and_i64 tcg_gen_and_i64_sparc64
#define tcg_gen_and_vec tcg_gen_and_vec_sparc64
#define tcg_gen_andc_i32 tcg_gen_andc_i32_sparc64
#define tcg_gen_andc_i64 tcg_gen_andc_i64_sparc64
#define tcg_gen_andc_vec tcg_gen_andc_vec_sparc64
#define tcg_gen_andi_i32 tcg_gen_andi_i32_sparc64
#define tcg_gen_andi_i64 tcg_gen_andi_i64_sparc64
#define tcg_gen_atomic_add_fetch_i32 tcg_gen_atomic_add_fetch_i32_sparc64
@ -3051,6 +3058,12 @@
#define tcg_gen_div_i64 tcg_gen_div_i64_sparc64
#define tcg_gen_divu_i32 tcg_gen_divu_i32_sparc64
#define tcg_gen_divu_i64 tcg_gen_divu_i64_sparc64
#define tcg_gen_dup8i_vec tcg_gen_dup8i_vec_sparc64
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_sparc64
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_sparc64
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_sparc64
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_sparc64
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_sparc64
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_sparc64
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_sparc64
#define tcg_gen_exit_tb tcg_gen_exit_tb_sparc64
@ -3082,12 +3095,14 @@
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_sparc64
#define tcg_gen_ld_i32 tcg_gen_ld_i32_sparc64
#define tcg_gen_ld_i64 tcg_gen_ld_i64_sparc64
#define tcg_gen_ld_vec tcg_gen_ld_vec_sparc64
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_sparc64
#define tcg_gen_ldst_op_i64 tcg_gen_ldst_op_i64_sparc64
#define tcg_gen_lookup_and_goto_ptr tcg_gen_lookup_and_goto_ptr_sparc64
#define tcg_gen_mb tcg_gen_mb_sparc64
#define tcg_gen_mov_i32 tcg_gen_mov_i32_sparc64
#define tcg_gen_mov_i64 tcg_gen_mov_i64_sparc64
#define tcg_gen_mov_vec tcg_gen_mov_vec_sparc64
#define tcg_gen_movcond_i32 tcg_gen_movcond_i32_sparc64
#define tcg_gen_movcond_i64 tcg_gen_movcond_i64_sparc64
#define tcg_gen_movi_i32 tcg_gen_movi_i32_sparc64
@ -3106,10 +3121,13 @@
#define tcg_gen_nand_i64 tcg_gen_nand_i64_sparc64
#define tcg_gen_neg_i32 tcg_gen_neg_i32_sparc64
#define tcg_gen_neg_i64 tcg_gen_neg_i64_sparc64
#define tcg_gen_neg_vec tcg_gen_neg_vec_sparc64
#define tcg_gen_nor_i32 tcg_gen_nor_i32_sparc64
#define tcg_gen_nor_i64 tcg_gen_nor_i64_sparc64
#define tcg_gen_nor_vec tcg_gen_nor_vec_sparc64
#define tcg_gen_not_i32 tcg_gen_not_i32_sparc64
#define tcg_gen_not_i64 tcg_gen_not_i64_sparc64
#define tcg_gen_not_vec tcg_gen_not_vec_sparc64
#define tcg_gen_op1 tcg_gen_op1_sparc64
#define tcg_gen_op1i tcg_gen_op1i_sparc64
#define tcg_gen_op2 tcg_gen_op2_sparc64
@ -3133,8 +3151,10 @@
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_sparc64
#define tcg_gen_or_i32 tcg_gen_or_i32_sparc64
#define tcg_gen_or_i64 tcg_gen_or_i64_sparc64
#define tcg_gen_or_vec tcg_gen_or_vec_sparc64
#define tcg_gen_orc_i32 tcg_gen_orc_i32_sparc64
#define tcg_gen_orc_i64 tcg_gen_orc_i64_sparc64
#define tcg_gen_orc_vec tcg_gen_orc_vec_sparc64
#define tcg_gen_ori_i32 tcg_gen_ori_i32_sparc64
#define tcg_gen_ori_i64 tcg_gen_ori_i64_sparc64
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_sparc64
@ -3174,16 +3194,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_sparc64
#define tcg_gen_st_i32 tcg_gen_st_i32_sparc64
#define tcg_gen_st_i64 tcg_gen_st_i64_sparc64
#define tcg_gen_st_vec tcg_gen_st_vec_sparc64
#define tcg_gen_stl_vec tcg_gen_stl_vec_sparc64
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_sparc64
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_sparc64
#define tcg_gen_sub_i32 tcg_gen_sub_i32_sparc64
#define tcg_gen_sub_i64 tcg_gen_sub_i64_sparc64
#define tcg_gen_sub_vec tcg_gen_sub_vec_sparc64
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_sparc64
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_sparc64
#define tcg_gen_subi_i32 tcg_gen_subi_i32_sparc64
#define tcg_gen_subi_i64 tcg_gen_subi_i64_sparc64
#define tcg_gen_xor_i32 tcg_gen_xor_i32_sparc64
#define tcg_gen_xor_i64 tcg_gen_xor_i64_sparc64
#define tcg_gen_xor_vec tcg_gen_xor_vec_sparc64
#define tcg_gen_xori_i32 tcg_gen_xori_i32_sparc64
#define tcg_gen_xori_i64 tcg_gen_xori_i64_sparc64
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_sparc64
@ -3290,6 +3314,7 @@
#define tcg_temp_alloc tcg_temp_alloc_sparc64
#define tcg_temp_free_i32 tcg_temp_free_i32_sparc64
#define tcg_temp_free_i64 tcg_temp_free_i64_sparc64
#define tcg_temp_free_vec tcg_temp_free_vec_sparc64
#define tcg_temp_free_internal tcg_temp_free_internal_sparc64
#define tcg_temp_local_new_i32 tcg_temp_local_new_i32_sparc64
#define tcg_temp_local_new_i64 tcg_temp_local_new_i64_sparc64
@ -3298,6 +3323,8 @@
#define tcg_temp_new_internal tcg_temp_new_internal_sparc64
#define tcg_temp_new_internal_i32 tcg_temp_new_internal_i32_sparc64
#define tcg_temp_new_internal_i64 tcg_temp_new_internal_i64_sparc64
#define tcg_temp_new_vec tcg_temp_new_vec_sparc64
#define tcg_temp_new_vec_matching tcg_temp_new_vec_matching_sparc64
#define tdb_hash tdb_hash_sparc64
#define teecr_write teecr_write_sparc64
#define teehbr_access teehbr_access_sparc64
@ -3395,6 +3422,9 @@
#define v8_el3_no_el2_cp_reginfo v8_el3_no_el2_cp_reginfo_sparc64
#define vapa_cp_reginfo vapa_cp_reginfo_sparc64
#define vbar_write vbar_write_sparc64
#define vec_gen_2 vec_gen_2_sparc64
#define vec_gen_3 vec_gen_3_sparc64
#define vec_gen_4 vec_gen_4_sparc64
#define vfp_exceptbits_from_host vfp_exceptbits_from_host_sparc64
#define vfp_exceptbits_to_host vfp_exceptbits_to_host_sparc64
#define vfp_get_fpcr vfp_get_fpcr_sparc64

49
qemu/tcg/README
View file

@ -498,6 +498,55 @@ of the memory access.
For a 32-bit host, qemu_ld/st_i64 is guaranteed to only be used with a
64-bit memory access specified in flags.
********* Host vector operations
All of the vector ops have two parameters, TCGOP_VECL & TCGOP_VECE.
The former specifies the length of the vector in log2 64-bit units; the
later specifies the length of the element (if applicable) in log2 8-bit units.
E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
* mov_vec v0, v1
* ld_vec v0, t1
* st_vec v0, t1
Move, load and store.
* dup_vec v0, r1
Duplicate the low N bits of R1 into VECL/VECE copies across V0.
* dupi_vec v0, c
Similarly, for a constant.
Smaller values will be replicated to host register size by the expanders.
* dup2_vec v0, r1, r2
Duplicate r2:r1 into VECL/64 copies across V0. This opcode is
only present for 32-bit hosts.
* add_vec v0, v1, v2
v0 = v1 + v2, in elements across the vector.
* sub_vec v0, v1, v2
Similarly, v0 = v1 - v2.
* neg_vec v0, v1
Similarly, v0 = -v1.
* and_vec v0, v1, v2
* or_vec v0, v1, v2
* xor_vec v0, v1, v2
* andc_vec v0, v1, v2
* orc_vec v0, v1, v2
* not_vec v0, v1
Similarly, logical operations with and without compliment.
Note that VECE is unused.
*********
Note 1: Some shortcuts are defined when the last operand is known to be

292
qemu/tcg/tcg-op-vec.c Normal file
View file

@ -0,0 +1,292 @@
/*
* Tiny Code Generator for QEMU
*
* Copyright (c) 2018 Linaro, Inc.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "tcg.h"
#include "tcg-op.h"
#include "tcg-mo.h"
/* Reduce the number of ifdefs below. This assumes that all uses of
TCGV_HIGH and TCGV_LOW are properly protected by a conditional that
the compiler can eliminate. */
#if TCG_TARGET_REG_BITS == 64
extern TCGv_i32 TCGV_LOW_link_error(TCGContext *, TCGv_i64);
extern TCGv_i32 TCGV_HIGH_link_error(TCGContext *, TCGv_i64);
#define TCGV_LOW TCGV_LOW_link_error
#define TCGV_HIGH TCGV_HIGH_link_error
#endif
void vec_gen_2(TCGContext *s, TCGOpcode opc, TCGType type, unsigned vece, TCGArg r, TCGArg a)
{
TCGOp *op = tcg_emit_op(s, opc);
TCGOP_VECL(op) = type - TCG_TYPE_V64;
TCGOP_VECE(op) = vece;
op->args[0] = r;
op->args[1] = a;
}
void vec_gen_3(TCGContext *s, TCGOpcode opc, TCGType type, unsigned vece,
TCGArg r, TCGArg a, TCGArg b)
{
TCGOp *op = tcg_emit_op(s, opc);
TCGOP_VECL(op) = type - TCG_TYPE_V64;
TCGOP_VECE(op) = vece;
op->args[0] = r;
op->args[1] = a;
op->args[2] = b;
}
void vec_gen_4(TCGContext *s, TCGOpcode opc, TCGType type, unsigned vece,
TCGArg r, TCGArg a, TCGArg b, TCGArg c)
{
TCGOp *op = tcg_emit_op(s, opc);
TCGOP_VECL(op) = type - TCG_TYPE_V64;
TCGOP_VECE(op) = vece;
op->args[0] = r;
op->args[1] = a;
op->args[2] = b;
op->args[3] = c;
}
static void vec_gen_op2(TCGContext *s, TCGOpcode opc, unsigned vece, TCGv_vec r, TCGv_vec a)
{
TCGTemp *rt = tcgv_vec_temp(s, r);
TCGTemp *at = tcgv_vec_temp(s, a);
TCGType type = rt->base_type;
tcg_debug_assert(at->base_type == type);
vec_gen_2(s, opc, type, vece, temp_arg(rt), temp_arg(at));
}
static void vec_gen_op3(TCGContext *s, TCGOpcode opc, unsigned vece,
TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
TCGTemp *rt = tcgv_vec_temp(s, r);
TCGTemp *at = tcgv_vec_temp(s, a);
TCGTemp *bt = tcgv_vec_temp(s, b);
TCGType type = rt->base_type;
tcg_debug_assert(at->base_type == type);
tcg_debug_assert(bt->base_type == type);
vec_gen_3(s, opc, type, vece, temp_arg(rt), temp_arg(at), temp_arg(bt));
}
void tcg_gen_mov_vec(TCGContext *s, TCGv_vec r, TCGv_vec a)
{
if (r != a) {
vec_gen_op2(s, INDEX_op_mov_vec, 0, r, a);
}
}
#define MO_REG (TCG_TARGET_REG_BITS == 64 ? MO_64 : MO_32)
static void tcg_gen_dupi_vec(TCGContext *s, TCGv_vec r, unsigned vece, TCGArg a)
{
TCGTemp *rt = tcgv_vec_temp(s, r);
vec_gen_2(s, INDEX_op_dupi_vec, rt->base_type, vece, temp_arg(rt), a);
}
TCGv_vec tcg_const_zeros_vec(TCGContext *s, TCGType type)
{
TCGv_vec ret = tcg_temp_new_vec(s, type);
tcg_gen_dupi_vec(s, ret, MO_REG, 0);
return ret;
}
TCGv_vec tcg_const_ones_vec(TCGContext *s, TCGType type)
{
TCGv_vec ret = tcg_temp_new_vec(s, type);
tcg_gen_dupi_vec(s, ret, MO_REG, -1);
return ret;
}
TCGv_vec tcg_const_zeros_vec_matching(TCGContext *s, TCGv_vec m)
{
TCGTemp *t = tcgv_vec_temp(s, m);
return tcg_const_zeros_vec(s, t->base_type);
}
TCGv_vec tcg_const_ones_vec_matching(TCGContext *s, TCGv_vec m)
{
TCGTemp *t = tcgv_vec_temp(s, m);
return tcg_const_ones_vec(s, t->base_type);
}
void tcg_gen_dup64i_vec(TCGContext *s, TCGv_vec r, uint64_t a)
{
if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) {
tcg_gen_dupi_vec(s, r, MO_32, a);
} else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) {
tcg_gen_dupi_vec(s, r, MO_64, a);
} else {
TCGv_i64 c = tcg_const_i64(s, a);
tcg_gen_dup_i64_vec(s, MO_64, r, c);
tcg_temp_free_i64(s, c);
}
}
void tcg_gen_dup32i_vec(TCGContext *s, TCGv_vec r, uint32_t a)
{
tcg_gen_dupi_vec(s, r, MO_REG, ((TCGArg)-1 / 0xffffffffu) * a);
}
void tcg_gen_dup16i_vec(TCGContext *s, TCGv_vec r, uint32_t a)
{
tcg_gen_dupi_vec(s, r, MO_REG, ((TCGArg)-1 / 0xffff) * (a & 0xffff));
}
void tcg_gen_dup8i_vec(TCGContext *s, TCGv_vec r, uint32_t a)
{
tcg_gen_dupi_vec(s, r, MO_REG, ((TCGArg)-1 / 0xff) * (a & 0xff));
}
void tcg_gen_dup_i64_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_i64 a)
{
TCGArg ri = tcgv_vec_arg(s, r);
TCGTemp *rt = arg_temp(ri);
TCGType type = rt->base_type;
if (TCG_TARGET_REG_BITS == 64) {
TCGArg ai = tcgv_i64_arg(s, a);
vec_gen_2(s, INDEX_op_dup_vec, type, MO_64, ri, ai);
} else if (vece == MO_64) {
TCGArg al = tcgv_i32_arg(s, TCGV_LOW(s, a));
TCGArg ah = tcgv_i32_arg(s, TCGV_HIGH(s, a));
vec_gen_3(s, INDEX_op_dup2_vec, type, MO_64, ri, al, ah);
} else {
TCGArg ai = tcgv_i32_arg(s, TCGV_LOW(s, a));
vec_gen_2(s, INDEX_op_dup_vec, type, MO_64, ri, ai);
}
}
void tcg_gen_dup_i32_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_i32 a)
{
TCGArg ri = tcgv_vec_arg(s, r);
TCGArg ai = tcgv_i32_arg(s, a);
TCGTemp *rt = arg_temp(ri);
TCGType type = rt->base_type;
vec_gen_2(s, INDEX_op_dup_vec, type, vece, ri, ai);
}
static void vec_gen_ldst(TCGContext *s, TCGOpcode opc, TCGv_vec r, TCGv_ptr b, TCGArg o)
{
TCGArg ri = tcgv_vec_arg(s, r);
TCGArg bi = tcgv_ptr_arg(s, b);
TCGTemp *rt = arg_temp(ri);
TCGType type = rt->base_type;
vec_gen_3(s, opc, type, 0, ri, bi, o);
}
void tcg_gen_ld_vec(TCGContext *s, TCGv_vec r, TCGv_ptr b, TCGArg o)
{
vec_gen_ldst(s, INDEX_op_ld_vec, r, b, o);
}
void tcg_gen_st_vec(TCGContext *s, TCGv_vec r, TCGv_ptr b, TCGArg o)
{
vec_gen_ldst(s, INDEX_op_st_vec, r, b, o);
}
void tcg_gen_stl_vec(TCGContext *s, TCGv_vec r, TCGv_ptr b, TCGArg o, TCGType low_type)
{
TCGArg ri = tcgv_vec_arg(s, r);
TCGArg bi = tcgv_ptr_arg(s, b);
TCGTemp *rt = arg_temp(ri);
TCGType type = rt->base_type;
tcg_debug_assert(low_type >= TCG_TYPE_V64);
tcg_debug_assert(low_type <= type);
vec_gen_3(s, INDEX_op_st_vec, low_type, 0, ri, bi, o);
}
void tcg_gen_add_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
vec_gen_op3(s, INDEX_op_add_vec, vece, r, a, b);
}
void tcg_gen_sub_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
vec_gen_op3(s, INDEX_op_sub_vec, vece, r, a, b);
}
void tcg_gen_and_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
vec_gen_op3(s, INDEX_op_and_vec, 0, r, a, b);
}
void tcg_gen_or_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
vec_gen_op3(s, INDEX_op_or_vec, 0, r, a, b);
}
void tcg_gen_xor_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
vec_gen_op3(s, INDEX_op_xor_vec, 0, r, a, b);
}
void tcg_gen_andc_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
if (TCG_TARGET_HAS_andc_vec) {
vec_gen_op3(s, INDEX_op_andc_vec, 0, r, a, b);
} else {
TCGv_vec t = tcg_temp_new_vec_matching(s, r);
tcg_gen_not_vec(s, 0, t, b);
tcg_gen_and_vec(s, 0, r, a, t);
tcg_temp_free_vec(s, t);
}
}
void tcg_gen_orc_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
if (TCG_TARGET_HAS_orc_vec) {
vec_gen_op3(s, INDEX_op_orc_vec, 0, r, a, b);
} else {
TCGv_vec t = tcg_temp_new_vec_matching(s, r);
tcg_gen_not_vec(s, 0, t, b);
tcg_gen_or_vec(s, 0, r, a, t);
tcg_temp_free_vec(s, t);
}
}
void tcg_gen_not_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a)
{
if (TCG_TARGET_HAS_not_vec) {
vec_gen_op2(s, INDEX_op_not_vec, 0, r, a);
} else {
TCGv_vec t = tcg_const_ones_vec_matching(s, r);
tcg_gen_xor_vec(s, 0, r, a, t);
tcg_temp_free_vec(s, t);
}
}
void tcg_gen_neg_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a)
{
if (TCG_TARGET_HAS_neg_vec) {
vec_gen_op2(s, INDEX_op_neg_vec, vece, r, a);
} else {
TCGv_vec t = tcg_const_zeros_vec_matching(s, r);
tcg_gen_sub_vec(s, vece, r, t, a);
tcg_temp_free_vec(s, t);
}
}

27
qemu/tcg/tcg-op.h
View file

@ -36,6 +36,10 @@ void tcg_gen_op5(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg,
void tcg_gen_op6(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg,
TCGArg, TCGArg, TCGArg);
void vec_gen_2(TCGContext *, TCGOpcode, TCGType, unsigned, TCGArg, TCGArg);
void vec_gen_3(TCGContext *, TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg);
void vec_gen_4(TCGContext *, TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg);
static inline void gen_uc_tracecode(TCGContext *tcg_ctx, int32_t size, int32_t type, void *uc, uint64_t pc)
{
TCGv_i32 tsize = tcg_const_i32(tcg_ctx, size);
@ -911,6 +915,27 @@ void tcg_gen_atomic_or_fetch_i64(TCGContext *, TCGv_i64, TCGv, TCGv_i64, TCGArg,
void tcg_gen_atomic_xor_fetch_i32(TCGContext *, TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
void tcg_gen_atomic_xor_fetch_i64(TCGContext *, TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
void tcg_gen_mov_vec(TCGContext *, TCGv_vec, TCGv_vec);
void tcg_gen_dup_i32_vec(TCGContext *, unsigned vece, TCGv_vec, TCGv_i32);
void tcg_gen_dup_i64_vec(TCGContext *, unsigned vece, TCGv_vec, TCGv_i64);
void tcg_gen_dup8i_vec(TCGContext *, TCGv_vec, uint32_t);
void tcg_gen_dup16i_vec(TCGContext *, TCGv_vec, uint32_t);
void tcg_gen_dup32i_vec(TCGContext *, TCGv_vec, uint32_t);
void tcg_gen_dup64i_vec(TCGContext *, TCGv_vec, uint64_t);
void tcg_gen_add_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_sub_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_and_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_or_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_xor_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_andc_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_orc_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_not_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a);
void tcg_gen_neg_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a);
void tcg_gen_ld_vec(TCGContext *, TCGv_vec r, TCGv_ptr base, TCGArg offset);
void tcg_gen_st_vec(TCGContext *, TCGv_vec r, TCGv_ptr base, TCGArg offset);
void tcg_gen_stl_vec(TCGContext *, TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
#if TARGET_LONG_BITS == 64
#define tcg_gen_movi_tl tcg_gen_movi_i64
#define tcg_gen_mov_tl tcg_gen_mov_i64
@ -1009,6 +1034,7 @@ void tcg_gen_atomic_xor_fetch_i64(TCGContext *, TCGv_i64, TCGv, TCGv_i64, TCGArg
#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64
#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64
#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64
#define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec
#else
#define tcg_gen_movi_tl tcg_gen_movi_i32
#define tcg_gen_mov_tl tcg_gen_mov_i32
@ -1106,6 +1132,7 @@ void tcg_gen_atomic_xor_fetch_i64(TCGContext *, TCGv_i64, TCGv, TCGv_i64, TCGArg
#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32
#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32
#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32
#define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec
#endif
#if UINTPTR_MAX == UINT32_MAX

23
qemu/tcg/tcg-opc.h
View file

@ -210,8 +210,31 @@ DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 1,
DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1,
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
#define IMPLVEC TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec)
DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT)
DEF(dupi_vec, 1, 0, 1, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT)
DEF(dup_vec, 1, 1, 0, IMPLVEC)
DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BITS == 32))
DEF(ld_vec, 1, 1, 1, IMPLVEC)
DEF(st_vec, 0, 2, 1, IMPLVEC)
DEF(add_vec, 1, 2, 0, IMPLVEC)
DEF(sub_vec, 1, 2, 0, IMPLVEC)
DEF(neg_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_neg_vec))
DEF(and_vec, 1, 2, 0, IMPLVEC)
DEF(or_vec, 1, 2, 0, IMPLVEC)
DEF(xor_vec, 1, 2, 0, IMPLVEC)
DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec))
DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec))
DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))
#undef TLADDR_ARGS
#undef DATA64_ARGS
#undef IMPL
#undef IMPL64
#undef IMPLVEC
#undef DEF

91
qemu/tcg/tcg.c
View file

@ -101,6 +101,18 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg ret, tcg_target_long arg);
static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
const int *const_args);
#if TCG_TARGET_MAYBE_vec
static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl,
unsigned vece, const TCGArg *args,
const int *const_args);
#else
static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl,
unsigned vece, const TCGArg *args,
const int *const_args)
{
g_assert_not_reached();
}
#endif
static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
intptr_t arg2);
static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
@ -685,6 +697,41 @@ TCGv_i64 tcg_temp_new_internal_i64(TCGContext *s, int temp_local)
return temp_tcgv_i64(s, t);
}
TCGv_vec tcg_temp_new_vec(TCGContext *s, TCGType type)
{
TCGTemp *t;
#ifdef CONFIG_DEBUG_TCG
switch (type) {
case TCG_TYPE_V64:
assert(TCG_TARGET_HAS_v64);
break;
case TCG_TYPE_V128:
assert(TCG_TARGET_HAS_v128);
break;
case TCG_TYPE_V256:
assert(TCG_TARGET_HAS_v256);
break;
default:
g_assert_not_reached();
}
#endif
t = tcg_temp_new_internal(s, type, 0);
return temp_tcgv_vec(s, t);
}
/* Create a new temp of the same type as an existing temp. */
TCGv_vec tcg_temp_new_vec_matching(TCGContext *s, TCGv_vec match)
{
TCGTemp *t = tcgv_vec_temp(s, match);
tcg_debug_assert(t->temp_allocated != 0);
t = tcg_temp_new_internal(s, t->base_type, 0);
return temp_tcgv_vec(s, t);
}
static void tcg_temp_free_internal(TCGContext *s, TCGTemp *ts)
{
int k, idx;
@ -715,6 +762,11 @@ void tcg_temp_free_i64(TCGContext *s, TCGv_i64 arg)
tcg_temp_free_internal(s, tcgv_i64_temp(s, arg));
}
void tcg_temp_free_vec(TCGContext *s, TCGv_vec arg)
{
tcg_temp_free_internal(s, tcgv_vec_temp(s, arg));
}
TCGv_i32 tcg_const_i32(TCGContext *s, int32_t val)
{
TCGv_i32 t0;
@ -770,6 +822,9 @@ int tcg_check_temp_count(TCGContext *s)
Test the runtime variable that controls each opcode. */
bool tcg_op_supported(TCGOpcode op)
{
const bool have_vec
= TCG_TARGET_HAS_v64 | TCG_TARGET_HAS_v128 | TCG_TARGET_HAS_v256;
switch (op) {
case INDEX_op_discard:
case INDEX_op_set_label:
@ -983,6 +1038,28 @@ bool tcg_op_supported(TCGOpcode op)
case INDEX_op_mulsh_i64:
return TCG_TARGET_HAS_mulsh_i64;
case INDEX_op_mov_vec:
case INDEX_op_dup_vec:
case INDEX_op_dupi_vec:
case INDEX_op_ld_vec:
case INDEX_op_st_vec:
case INDEX_op_add_vec:
case INDEX_op_sub_vec:
case INDEX_op_and_vec:
case INDEX_op_or_vec:
case INDEX_op_xor_vec:
return have_vec;
case INDEX_op_dup2_vec:
return have_vec && TCG_TARGET_REG_BITS == 32;
case INDEX_op_not_vec:
return have_vec && TCG_TARGET_HAS_not_vec;
case INDEX_op_neg_vec:
return have_vec && TCG_TARGET_HAS_neg_vec;
case INDEX_op_andc_vec:
return have_vec && TCG_TARGET_HAS_andc_vec;
case INDEX_op_orc_vec:
return have_vec && TCG_TARGET_HAS_orc_vec;
case NB_OPS:
break;
}
@ -1349,6 +1426,11 @@ void tcg_dump_ops(TCGContext *s)
nb_iargs = TCGOP_CALLI(op);
nb_cargs = def->nb_cargs;
if (def->flags & TCG_OPF_VECTOR) {
col += qemu_log("v%d,e%d,", 64 << TCGOP_VECL(op),
8 << TCGOP_VECE(op));
}
/* function name, flags, out args */
col += qemu_log(" %s %s,$0x%" TCG_PRIlx ",$%d", def->name,
tcg_find_helper(s, op->args[nb_oargs + nb_iargs]),
@ -2638,7 +2720,12 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
}
/* emit instruction */
tcg_out_op(s, op->opc, new_args, const_args);
if (def->flags & TCG_OPF_VECTOR) {
tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op),
new_args, const_args);
} else {
tcg_out_op(s, op->opc, new_args, const_args);
}
/* move the outputs in the correct register if needed */
for(i = 0; i < nb_oargs; i++) {
@ -2907,10 +2994,12 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
switch (opc) {
case INDEX_op_mov_i32:
case INDEX_op_mov_i64:
case INDEX_op_mov_vec:
tcg_reg_alloc_mov(s, op);
break;
case INDEX_op_movi_i32:
case INDEX_op_movi_i64:
case INDEX_op_dupi_vec:
tcg_reg_alloc_movi(s, op);
break;
case INDEX_op_insn_start:

60
qemu/tcg/tcg.h
View file

@ -173,6 +173,27 @@ typedef uint64_t TCGRegSet;
# error "Missing unsigned widening multiply"
#endif
#if !defined(TCG_TARGET_HAS_v64) \
&& !defined(TCG_TARGET_HAS_v128) \
&& !defined(TCG_TARGET_HAS_v256)
#define TCG_TARGET_MAYBE_vec 0
#define TCG_TARGET_HAS_neg_vec 0
#define TCG_TARGET_HAS_not_vec 0
#define TCG_TARGET_HAS_andc_vec 0
#define TCG_TARGET_HAS_orc_vec 0
#else
#define TCG_TARGET_MAYBE_vec 1
#endif
#ifndef TCG_TARGET_HAS_v64
#define TCG_TARGET_HAS_v64 0
#endif
#ifndef TCG_TARGET_HAS_v128
#define TCG_TARGET_HAS_v128 0
#endif
#ifndef TCG_TARGET_HAS_v256
#define TCG_TARGET_HAS_v256 0
#endif
#ifndef TARGET_INSN_START_EXTRA_WORDS
# define TARGET_INSN_START_WORDS 1
#else
@ -248,6 +269,11 @@ typedef struct TCGPool {
typedef enum TCGType {
TCG_TYPE_I32,
TCG_TYPE_I64,
TCG_TYPE_V64,
TCG_TYPE_V128,
TCG_TYPE_V256,
TCG_TYPE_COUNT, /* number of different types */
/* An alias for the size of the host register. */
@ -399,6 +425,8 @@ typedef tcg_target_ulong TCGArg;
* TCGv_i32 : 32 bit integer type
* TCGv_i64 : 64 bit integer type
* TCGv_ptr : a host pointer type
* TCGv_vec : a host vector type; the exact size is not exposed
to the CPU front-end code.
* TCGv : an integer type the same size as target_ulong
(an alias for either TCGv_i32 or TCGv_i64)
The compiler's type checking will complain if you mix them
@ -421,6 +449,7 @@ typedef tcg_target_ulong TCGArg;
typedef struct TCGv_i32_d *TCGv_i32;
typedef struct TCGv_i64_d *TCGv_i64;
typedef struct TCGv_ptr_d *TCGv_ptr;
typedef struct TCGv_vec_d *TCGv_vec;
typedef TCGv_ptr TCGv_env;
#if TARGET_LONG_BITS == 32
#define TCGv TCGv_i32
@ -593,6 +622,9 @@ typedef struct TCGOp {
#define TCGOP_CALLI(X) (X)->param1
#define TCGOP_CALLO(X) (X)->param2
#define TCGOP_VECL(X) (X)->param1
#define TCGOP_VECE(X) (X)->param2
/* Make sure operands fit in the bitfields above. */
QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8));
@ -657,6 +689,8 @@ enum {
/* Instruction is optional and not implemented by the host, or insn
is generic and should not be implemened by the host. */
TCG_OPF_NOT_PRESENT = 0x10,
/* Instruction operands are vectors. */
TCG_OPF_VECTOR = 0x20,
};
typedef struct TCGOpDef {
@ -808,7 +842,7 @@ struct TCGContext {
/* qemu/tcg/tcg.c */
uint64_t tcg_target_call_clobber_regs;
uint64_t tcg_target_available_regs[2];
uint64_t tcg_target_available_regs[TCG_TYPE_COUNT];
// Unicorn: Use a large array size to get around needing a file static
// Initially was using: ARRAY_SIZE(tcg_target_reg_alloc_order) as the size
int indirect_reg_alloc_order[50];
@ -935,6 +969,11 @@ static inline TCGTemp *tcgv_ptr_temp(TCGContext *s, TCGv_ptr v)
return tcgv_i32_temp(s, (TCGv_i32)v);
}
static inline TCGTemp *tcgv_vec_temp(TCGContext *s, TCGv_vec v)
{
return tcgv_i32_temp(s, (TCGv_i32)v);
}
static inline TCGArg tcgv_i32_arg(TCGContext *s, TCGv_i32 v)
{
return temp_arg(tcgv_i32_temp(s, v));
@ -950,6 +989,11 @@ static inline TCGArg tcgv_ptr_arg(TCGContext *s, TCGv_ptr v)
return temp_arg(tcgv_ptr_temp(s, v));
}
static inline TCGArg tcgv_vec_arg(TCGContext *s, TCGv_vec v)
{
return temp_arg(tcgv_vec_temp(s, v));
}
static inline TCGv_i32 temp_tcgv_i32(TCGContext *s, TCGTemp *t)
{
(void)temp_idx(s, t); /* trigger embedded assert */
@ -966,6 +1010,11 @@ static inline TCGv_ptr temp_tcgv_ptr(TCGContext *s, TCGTemp *t)
return (TCGv_ptr)temp_tcgv_i32(s, t);
}
static inline TCGv_vec temp_tcgv_vec(TCGContext *s, TCGTemp *t)
{
return (TCGv_vec)temp_tcgv_i32(s, t);
}
#if TCG_TARGET_REG_BITS == 32
static inline TCGv_i32 TCGV_LOW(TCGContext *s, TCGv_i64 t)
{
@ -1003,9 +1052,12 @@ TCGv_i64 tcg_global_reg_new_i64(TCGContext *s, TCGReg reg, const char *name);
TCGv_i32 tcg_temp_new_internal_i32(TCGContext *s, int temp_local);
TCGv_i64 tcg_temp_new_internal_i64(TCGContext *s, int temp_local);
TCGv_vec tcg_temp_new_vec(TCGContext *s, TCGType type);
TCGv_vec tcg_temp_new_vec_matching(TCGContext *s, TCGv_vec match);
void tcg_temp_free_i32(TCGContext *s, TCGv_i32 arg);
void tcg_temp_free_i64(TCGContext *s, TCGv_i64 arg);
void tcg_temp_free_vec(TCGContext *s, TCGv_vec arg);
static inline TCGv_i32 tcg_global_mem_new_i32(TCGContext *s, TCGv_ptr reg,
intptr_t offset, const char *name)
@ -1042,7 +1094,7 @@ static inline TCGv_i64 tcg_temp_local_new_i64(TCGContext *s)
}
// UNICORN: Added
#define TCG_OP_DEFS_TABLE_SIZE 136
#define TCG_OP_DEFS_TABLE_SIZE 151
extern const TCGOpDef tcg_op_defs_org[TCG_OP_DEFS_TABLE_SIZE];
typedef struct TCGTargetOpDef {
@ -1116,6 +1168,10 @@ TCGv_i32 tcg_const_i32(TCGContext *s, int32_t val);
TCGv_i64 tcg_const_i64(TCGContext *s, int64_t val);
TCGv_i32 tcg_const_local_i32(TCGContext *s, int32_t val);
TCGv_i64 tcg_const_local_i64(TCGContext *s, int64_t val);
TCGv_vec tcg_const_zeros_vec(TCGContext *s, TCGType);
TCGv_vec tcg_const_ones_vec(TCGContext *s, TCGType);
TCGv_vec tcg_const_zeros_vec_matching(TCGContext *s, TCGv_vec);
TCGv_vec tcg_const_ones_vec_matching(TCGContext *s, TCGv_vec);
TCGLabel *gen_new_label(TCGContext* s);

30
qemu/x86_64.h
View file

@ -2971,6 +2971,10 @@
#define tcg_const_i64 tcg_const_i64_x86_64
#define tcg_const_local_i32 tcg_const_local_i32_x86_64
#define tcg_const_local_i64 tcg_const_local_i64_x86_64
#define tcg_const_ones_vec tcg_const_ones_vec_x86_64
#define tcg_const_ones_vec_matching tcg_const_ones_vec_matching_x86_64
#define tcg_const_zeros_vec tcg_const_zeros_vec_x86_64
#define tcg_const_zeros_vec_matching tcg_const_zeros_vec_matching_x86_64
#define tcg_constant_folding tcg_constant_folding_x86_64
#define tcg_context_init tcg_context_init_x86_64
#define tcg_cpu_exec tcg_cpu_exec_x86_64
@ -2989,12 +2993,15 @@
#define tcg_gen_add2_i64 tcg_gen_add2_i64_x86_64
#define tcg_gen_add_i32 tcg_gen_add_i32_x86_64
#define tcg_gen_add_i64 tcg_gen_add_i64_x86_64
#define tcg_gen_add_vec tcg_gen_add_vec_x86_64
#define tcg_gen_addi_i32 tcg_gen_addi_i32_x86_64
#define tcg_gen_addi_i64 tcg_gen_addi_i64_x86_64
#define tcg_gen_and_i32 tcg_gen_and_i32_x86_64
#define tcg_gen_and_i64 tcg_gen_and_i64_x86_64
#define tcg_gen_and_vec tcg_gen_and_vec_x86_64
#define tcg_gen_andc_i32 tcg_gen_andc_i32_x86_64
#define tcg_gen_andc_i64 tcg_gen_andc_i64_x86_64
#define tcg_gen_andc_vec tcg_gen_andc_vec_x86_64
#define tcg_gen_andi_i32 tcg_gen_andi_i32_x86_64
#define tcg_gen_andi_i64 tcg_gen_andi_i64_x86_64
#define tcg_gen_atomic_add_fetch_i32 tcg_gen_atomic_add_fetch_i32_x86_64
@ -3051,6 +3058,12 @@
#define tcg_gen_div_i64 tcg_gen_div_i64_x86_64
#define tcg_gen_divu_i32 tcg_gen_divu_i32_x86_64
#define tcg_gen_divu_i64 tcg_gen_divu_i64_x86_64
#define tcg_gen_dup8i_vec tcg_gen_dup8i_vec_x86_64
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_x86_64
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_x86_64
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_x86_64
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_x86_64
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_x86_64
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_x86_64
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_x86_64
#define tcg_gen_exit_tb tcg_gen_exit_tb_x86_64
@ -3082,12 +3095,14 @@
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_x86_64
#define tcg_gen_ld_i32 tcg_gen_ld_i32_x86_64
#define tcg_gen_ld_i64 tcg_gen_ld_i64_x86_64
#define tcg_gen_ld_vec tcg_gen_ld_vec_x86_64
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_x86_64
#define tcg_gen_ldst_op_i64 tcg_gen_ldst_op_i64_x86_64
#define tcg_gen_lookup_and_goto_ptr tcg_gen_lookup_and_goto_ptr_x86_64
#define tcg_gen_mb tcg_gen_mb_x86_64
#define tcg_gen_mov_i32 tcg_gen_mov_i32_x86_64
#define tcg_gen_mov_i64 tcg_gen_mov_i64_x86_64
#define tcg_gen_mov_vec tcg_gen_mov_vec_x86_64
#define tcg_gen_movcond_i32 tcg_gen_movcond_i32_x86_64
#define tcg_gen_movcond_i64 tcg_gen_movcond_i64_x86_64
#define tcg_gen_movi_i32 tcg_gen_movi_i32_x86_64
@ -3106,10 +3121,13 @@
#define tcg_gen_nand_i64 tcg_gen_nand_i64_x86_64
#define tcg_gen_neg_i32 tcg_gen_neg_i32_x86_64
#define tcg_gen_neg_i64 tcg_gen_neg_i64_x86_64
#define tcg_gen_neg_vec tcg_gen_neg_vec_x86_64
#define tcg_gen_nor_i32 tcg_gen_nor_i32_x86_64
#define tcg_gen_nor_i64 tcg_gen_nor_i64_x86_64
#define tcg_gen_nor_vec tcg_gen_nor_vec_x86_64
#define tcg_gen_not_i32 tcg_gen_not_i32_x86_64
#define tcg_gen_not_i64 tcg_gen_not_i64_x86_64
#define tcg_gen_not_vec tcg_gen_not_vec_x86_64
#define tcg_gen_op1 tcg_gen_op1_x86_64
#define tcg_gen_op1i tcg_gen_op1i_x86_64
#define tcg_gen_op2 tcg_gen_op2_x86_64
@ -3133,8 +3151,10 @@
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_x86_64
#define tcg_gen_or_i32 tcg_gen_or_i32_x86_64
#define tcg_gen_or_i64 tcg_gen_or_i64_x86_64
#define tcg_gen_or_vec tcg_gen_or_vec_x86_64
#define tcg_gen_orc_i32 tcg_gen_orc_i32_x86_64
#define tcg_gen_orc_i64 tcg_gen_orc_i64_x86_64
#define tcg_gen_orc_vec tcg_gen_orc_vec_x86_64
#define tcg_gen_ori_i32 tcg_gen_ori_i32_x86_64
#define tcg_gen_ori_i64 tcg_gen_ori_i64_x86_64
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_x86_64
@ -3174,16 +3194,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_x86_64
#define tcg_gen_st_i32 tcg_gen_st_i32_x86_64
#define tcg_gen_st_i64 tcg_gen_st_i64_x86_64
#define tcg_gen_st_vec tcg_gen_st_vec_x86_64
#define tcg_gen_stl_vec tcg_gen_stl_vec_x86_64
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_x86_64
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_x86_64
#define tcg_gen_sub_i32 tcg_gen_sub_i32_x86_64
#define tcg_gen_sub_i64 tcg_gen_sub_i64_x86_64
#define tcg_gen_sub_vec tcg_gen_sub_vec_x86_64
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_x86_64
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_x86_64
#define tcg_gen_subi_i32 tcg_gen_subi_i32_x86_64
#define tcg_gen_subi_i64 tcg_gen_subi_i64_x86_64
#define tcg_gen_xor_i32 tcg_gen_xor_i32_x86_64
#define tcg_gen_xor_i64 tcg_gen_xor_i64_x86_64
#define tcg_gen_xor_vec tcg_gen_xor_vec_x86_64
#define tcg_gen_xori_i32 tcg_gen_xori_i32_x86_64
#define tcg_gen_xori_i64 tcg_gen_xori_i64_x86_64
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_x86_64
@ -3290,6 +3314,7 @@
#define tcg_temp_alloc tcg_temp_alloc_x86_64
#define tcg_temp_free_i32 tcg_temp_free_i32_x86_64
#define tcg_temp_free_i64 tcg_temp_free_i64_x86_64
#define tcg_temp_free_vec tcg_temp_free_vec_x86_64
#define tcg_temp_free_internal tcg_temp_free_internal_x86_64
#define tcg_temp_local_new_i32 tcg_temp_local_new_i32_x86_64
#define tcg_temp_local_new_i64 tcg_temp_local_new_i64_x86_64
@ -3298,6 +3323,8 @@
#define tcg_temp_new_internal tcg_temp_new_internal_x86_64
#define tcg_temp_new_internal_i32 tcg_temp_new_internal_i32_x86_64
#define tcg_temp_new_internal_i64 tcg_temp_new_internal_i64_x86_64
#define tcg_temp_new_vec tcg_temp_new_vec_x86_64
#define tcg_temp_new_vec_matching tcg_temp_new_vec_matching_x86_64
#define tdb_hash tdb_hash_x86_64
#define teecr_write teecr_write_x86_64
#define teehbr_access teehbr_access_x86_64
@ -3395,6 +3422,9 @@
#define v8_el3_no_el2_cp_reginfo v8_el3_no_el2_cp_reginfo_x86_64
#define vapa_cp_reginfo vapa_cp_reginfo_x86_64
#define vbar_write vbar_write_x86_64
#define vec_gen_2 vec_gen_2_x86_64
#define vec_gen_3 vec_gen_3_x86_64
#define vec_gen_4 vec_gen_4_x86_64
#define vfp_exceptbits_from_host vfp_exceptbits_from_host_x86_64
#define vfp_exceptbits_to_host vfp_exceptbits_to_host_x86_64
#define vfp_get_fpcr vfp_get_fpcr_x86_64