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target/arm: [tcg] Port to insn_start

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Incrementally paves the way towards using the generic instruction translation
loop.

Backports commit f62bd897e64c6fb1f93e8795e835980516fe53b5 from qemu
This commit is contained in:
Lluís Vilanova 2018-03-04 19:24:42 -05:00 committed by Lioncash
parent b3878f117e
commit b9df4e0ca0
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 12 additions and 4 deletions
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16
qemu/target/arm/translate.c
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@ -12146,6 +12146,17 @@ static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
}
}
static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
TCGContext *tcg_ctx = cpu->uc->tcg_ctx;
dc->insn_start_idx = tcg_op_buf_count(tcg_ctx);
tcg_gen_insn_start(tcg_ctx, dc->pc,
(dc->condexec_cond << 4) | (dc->condexec_mask >> 1),
0);
}
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
{
@ -12211,10 +12222,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
do {
dc->base.num_insns++;
dc->insn_start_idx = tcg_op_buf_count(tcg_ctx);
tcg_gen_insn_start(tcg_ctx, dc->pc,
(dc->condexec_cond << 4) | (dc->condexec_mask >> 1),
0);
arm_tr_insn_start(&dc->base, cs);
if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
CPUBreakpoint *bp;