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target-mips: change ASID type to hold more than 8 bits

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ASID currently has uint8_t type which is too small since some processors
support more than 8 bits ASID. Therefore change its type to uint16_t.

Backports commit 2d72e7b047d800c9f99262466f65a98684ecca14 from qemu
This commit is contained in:
Paul Burton 2018-02-25 03:48:08 -05:00 committed by Lioncash
parent ac27c881ff
commit ba4dcc8c2f
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GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 7 additions and 7 deletions
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2
qemu/target-mips/cpu.h
View file

@ -20,7 +20,7 @@ typedef struct r4k_tlb_t r4k_tlb_t;
struct r4k_tlb_t { struct r4k_tlb_t {
target_ulong VPN; target_ulong VPN;
uint32_t PageMask; uint32_t PageMask;
uint8_t ASID; uint16_t ASID;
uint16_t G:1; uint16_t G:1;
uint16_t C0:3; uint16_t C0:3;
uint16_t C1:3; uint16_t C1:3;

4
qemu/target-mips/helper.c
View file

@ -67,7 +67,7 @@ int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
target_ulong address, int rw, int access_type) target_ulong address, int rw, int access_type)
{ {
uint8_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
int i; int i;
for (i = 0; i < env->tlb->tlb_in_use; i++) { for (i = 0; i < env->tlb->tlb_in_use; i++) {
@ -887,7 +887,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
r4k_tlb_t *tlb; r4k_tlb_t *tlb;
target_ulong addr; target_ulong addr;
target_ulong end; target_ulong end;
uint8_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
target_ulong mask; target_ulong mask;
tlb = &env->tlb->mmu.r4k.tlb[idx]; tlb = &env->tlb->mmu.r4k.tlb[idx];

8
qemu/target-mips/op_helper.c
View file

@ -2002,7 +2002,7 @@ void r4k_helper_tlbinv(CPUMIPSState *env)
{ {
int idx; int idx;
r4k_tlb_t *tlb; r4k_tlb_t *tlb;
uint8_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
for (idx = 0; idx < env->tlb->nb_tlb; idx++) { for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
tlb = &env->tlb->mmu.r4k.tlb[idx]; tlb = &env->tlb->mmu.r4k.tlb[idx];
@ -2028,7 +2028,7 @@ void r4k_helper_tlbwi(CPUMIPSState *env)
r4k_tlb_t *tlb; r4k_tlb_t *tlb;
int idx; int idx;
target_ulong VPN; target_ulong VPN;
uint8_t ASID; uint16_t ASID;
bool G, V0, D0, V1, D1; bool G, V0, D0, V1, D1;
idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
@ -2070,7 +2070,7 @@ void r4k_helper_tlbp(CPUMIPSState *env)
target_ulong mask; target_ulong mask;
target_ulong tag; target_ulong tag;
target_ulong VPN; target_ulong VPN;
uint8_t ASID; uint16_t ASID;
int i; int i;
ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
@ -2125,7 +2125,7 @@ static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
void r4k_helper_tlbr(CPUMIPSState *env) void r4k_helper_tlbr(CPUMIPSState *env)
{ {
r4k_tlb_t *tlb; r4k_tlb_t *tlb;
uint8_t ASID; uint16_t ASID;
int idx; int idx;
ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;