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target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h
Backports 2a14526a6f56973348d622abc572db377f5a23ef
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@ -1600,6 +1600,37 @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
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/*
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* System register ID fields.
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*/
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FIELD(CLIDR_EL1, CTYPE1, 0, 3)
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FIELD(CLIDR_EL1, CTYPE2, 3, 3)
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FIELD(CLIDR_EL1, CTYPE3, 6, 3)
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FIELD(CLIDR_EL1, CTYPE4, 9, 3)
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FIELD(CLIDR_EL1, CTYPE5, 12, 3)
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FIELD(CLIDR_EL1, CTYPE6, 15, 3)
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FIELD(CLIDR_EL1, CTYPE7, 18, 3)
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FIELD(CLIDR_EL1, LOUIS, 21, 3)
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FIELD(CLIDR_EL1, LOC, 24, 3)
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FIELD(CLIDR_EL1, LOUU, 27, 3)
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FIELD(CLIDR_EL1, ICB, 30, 3)
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/* When FEAT_CCIDX is implemented */
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FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
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FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
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FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
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/* When FEAT_CCIDX is not implemented */
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FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
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FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
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FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
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FIELD(CTR_EL0, IMINLINE, 0, 4)
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FIELD(CTR_EL0, L1IP, 14, 2)
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FIELD(CTR_EL0, DMINLINE, 16, 4)
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FIELD(CTR_EL0, ERG, 20, 4)
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FIELD(CTR_EL0, CWG, 24, 4)
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FIELD(CTR_EL0, IDC, 28, 1)
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FIELD(CTR_EL0, DIC, 29, 1)
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FIELD(CTR_EL0, TMINLINE, 32, 6)
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FIELD(MIDR_EL1, REVISION, 0, 4)
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FIELD(MIDR_EL1, PARTNUM, 4, 12)
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FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
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