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https://github.com/yuzu-emu/unicorn.git
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target/arm/cpu and crypto_helper: Correct bad merge and adjust to qemu code style
This commit is contained in:
Lioncash
parent
0751366e5c
commit
bab31a2510
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@ -115,7 +115,6 @@ enum {
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#define ARM_CPU_VFIQ 3
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#define NB_MMU_MODES 8
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/* ARM-specific extra insn start words:
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* 1: Conditional execution bits
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* 2: Partial exception syndrome for data aborts
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@ -199,6 +198,7 @@ typedef struct ARMPredicateReg {
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} ARMPredicateReg;
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#endif
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typedef struct CPUARMState {
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/* Regs for current mode. */
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uint32_t regs[16];
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@ -248,7 +248,7 @@ typedef struct CPUARMState {
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uint32_t GE; /* cpsr[19:16] */
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uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
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uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
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uint64_t daif; /* exception masks, in the bits they are in in PSTATE */
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uint64_t daif; /* exception masks, in the bits they are in PSTATE */
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uint64_t elr_el[4]; /* AArch64 exception link regs */
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uint64_t sp_el[4]; /* AArch64 banked stack pointers */
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@ -301,8 +301,8 @@ typedef struct CPUARMState {
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/* MMU translation table base control. */
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TCR tcr_el[4];
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TCR vtcr_el2; /* Virtualization Translation Control. */
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uint32_t c2_data; /* MPU data cachable bits. */
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uint32_t c2_insn; /* MPU instruction cachable bits. */
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uint32_t c2_data; /* MPU data cacheable bits. */
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uint32_t c2_insn; /* MPU instruction cacheable bits. */
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union { /* MMU domain access control register
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* MPU write buffer control.
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*/
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@ -631,8 +631,7 @@ typedef struct CPUARMState {
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void *nvic;
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const struct arm_boot_info *boot_info;
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// Store GICv3State to access from this struct
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/* Store GICv3CPUState to access from this struct */
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void *gicv3state;
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// Unicorn engine
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@ -646,6 +645,7 @@ typedef struct CPUARMState {
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*/
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typedef void ARMELChangeHook(ARMCPU *cpu, void *opaque);
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/* These values map onto the return values for
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* QEMU_PSCI_0_2_FN_AFFINITY_INFO */
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typedef enum ARMPSCIState {
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@ -1481,7 +1481,6 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el)
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{
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/* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want,
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* and if we're not in EL0 then the state of EL0 isn't well defined.)
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* then the state of EL0 isn't well defined.)
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*/
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assert(el >= 1 && el <= 3);
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bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
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@ -1509,7 +1508,7 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el)
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return aa64;
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}
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/* Function for determining whether guest cp register reads and writes should
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/* Function for determing whether guest cp register reads and writes should
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* access the secure or non-secure bank of a cp register. When EL3 is
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* operating in AArch32 state, the NS-bit determines whether the secure
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* instance of a cp register should be used. When EL3 is AArch64 (or if
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@ -1525,7 +1524,6 @@ static inline bool access_secure_reg(CPUARMState *env)
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return ret;
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}
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/* Macros for accessing a specified CP register bank */
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#define A32_BANKED_REG_GET(_env, _regname, _secure) \
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((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
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@ -1566,7 +1564,19 @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
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return true;
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}
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#endif
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void armv7m_nvic_set_pending(void *opaque, int irq);
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/**
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* armv7m_nvic_set_pending: mark the specified exception as pending
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* @opaque: the NVIC
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* @irq: the exception number to mark pending
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* @secure: false for non-banked exceptions or for the nonsecure
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* version of a banked exception, true for the secure version of a banked
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* exception.
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*
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* Marks the specified exception as pending. Note that we will assert()
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* if @secure is true and @irq does not specify one of the fixed set
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* of architecturally banked exceptions.
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*/
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void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
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/**
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* armv7m_nvic_set_pending_derived: mark this derived exception as pending
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* @opaque: the NVIC
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@ -1595,28 +1605,27 @@ void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
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*/
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void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
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bool *ptargets_secure);
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/**
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/**
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* armv7m_nvic_acknowledge_irq: make highest priority pending exception active
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* @opaque: the NVIC
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*
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* Move the current highest priority pending exception from the pending
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* state to the active state, and update v7m.exception to indicate that
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* it is the exception currently being handled.
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*
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* Returns: true if exception should be taken to Secure state, false for NS
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*/
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void armv7m_nvic_acknowledge_irq(void *opaque);
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/**
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* armv7m_nvic_complete_irq: complete specified interrupt or exception
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* @opaque: the NVIC
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* @irq: the exception number to complete
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* @secure: true if this exception was secure
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*
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* Returns: -1 if the irq was not active
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* 1 if completing this irq brought us back to base (no active irqs)
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* 0 if there is still an irq active after this one was completed
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* (Ignoring -1, this is the same as the RETTOBASE value before completion.)
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*/
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int armv7m_nvic_complete_irq(void *opaque, int irq);
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int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
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/**
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* armv7m_nvic_raw_execution_priority: return the raw execution priority
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* @opaque: the NVIC
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@ -2171,6 +2180,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
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case EXCP_FIQ:
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pstate_unmasked = !(env->daif & PSTATE_F);
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break;
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case EXCP_IRQ:
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pstate_unmasked = !(env->daif & PSTATE_I);
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break;
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@ -2252,7 +2262,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
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}
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}
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/* The PSTATE bits only mask the interrupt if we have not overridden the
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/* The PSTATE bits only mask the interrupt if we have not overriden the
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* ability above.
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*/
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return unmasked || pstate_unmasked;
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@ -2428,12 +2438,6 @@ static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx)
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}
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}
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/* Indexes used when registering address spaces with cpu_address_space_init */
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typedef enum ARMASIdx {
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ARMASIdx_NS = 0,
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ARMASIdx_S = 1,
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} ARMASIdx;
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/* Return the exception level we're running at if this is our mmu_idx */
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static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
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{
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@ -2500,6 +2504,12 @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
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return el;
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}
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/* Indexes used when registering address spaces with cpu_address_space_init */
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typedef enum ARMASIdx {
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ARMASIdx_NS = 0,
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ARMASIdx_S = 1,
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} ARMASIdx;
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/* Return the Exception Level targeted by debug exceptions. */
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static inline int arm_debug_target_el(CPUARMState *env)
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{
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@ -34,7 +34,6 @@ void HELPER(crypto_aese)(void *vd, void *vm, uint32_t decrypt)
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{
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static uint8_t const * const sbox[2] = { AES_sbox, AES_isbox };
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static uint8_t const * const shift[2] = { AES_shifts, AES_ishifts };
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uint64_t *rd = vd;
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uint64_t *rm = vm;
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union CRYPTO_STATE rk;
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@ -350,13 +349,13 @@ static uint32_t s1(uint32_t x)
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void HELPER(crypto_sha256h)(void *vd, void *vn, void *vm)
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{
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int i;
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uint64_t *rd = vd;
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uint64_t *rn = vn;
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uint64_t *rm = vm;
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union CRYPTO_STATE d;
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union CRYPTO_STATE n;
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union CRYPTO_STATE m;
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int i;
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d.l[0] = rd[0];
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d.l[1] = rd[1];
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n.l[0] = rn[0];
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