target/mips: Introduce 32 R5900 multimedia registers

The 32 R5900 128-bit registers are split into two 64-bit halves:
the lower halves are the GPRs and the upper halves are accessible
by the R5900-specific multimedia instructions.

Backports commit a168a796e1c251787fcdf2d9ca1e9e69cb86ffcd from qemu

qemu/target/mips/cpu.h

@@ -429,6 +429,9 @@ struct TCState {
 
     float_status msa_fp_status;
 
+    /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */
+    uint64_t mmr[32];
+
 #define NUMBER_OF_MXU_REGISTERS 16
     target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
     target_ulong mxu_cr;

qemu/target/mips/translate.c

@@ -30034,6 +30034,16 @@ void mips_tcg_init(struct uc_struct *uc)
                                        offsetof(CPUMIPSState, active_fpu.fcr31),
                                        "fcr31");
 
+#if defined(TARGET_MIPS64)
+    tcg_ctx->cpu_mmr[0] = NULL;
+    for (i = 1; i < 32; i++) {
+        tcg_ctx->cpu_mmr[i] = tcg_global_mem_new_i64(tcg_ctx, tcg_ctx->cpu_env,
+                                                     offsetof(CPUMIPSState,
+                                                        active_tc.mmr[i]),
+                                                     regnames[i]);
+    }
+#endif
+
 #if !defined(TARGET_MIPS64)
     for (i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) {
         tcg_ctx->mxu_gpr[i] = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,

qemu/tcg/tcg.h

@@ -904,6 +904,9 @@ struct TCGContext {
     TCGv mxu_gpr[16 - 1]; // NUMBER_OF_MXU_REGISTERS - 1
     TCGv mxu_CR;
 
+    /* Upper halves of R5900's 128-bit registers: MMRs (multimedia registers) */
+    TCGv_i64 cpu_mmr[32];
+
     /* qemu/target-sparc/translate.c */
     /* global register indexes */
     TCGv_ptr cpu_regwptr;