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target-mips: fix EntryHi.EHINV being cleared on TLB exception

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While implementing TLB invalidation feature we forgot to modify
part of code responsible for updating EntryHi during TLB exception.
Consequently EntryHi.EHINV is unexpectedly cleared on the exception.

Backports commit 701074a6fc7470d0ed54e4a4bcd4d491ad8da22e from qemu
This commit is contained in:
Leon Alrae 2018-02-25 21:02:25 -05:00 committed by Lioncash
parent 943b9fc261
commit bc434da124
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1 changed files with 1 additions and 0 deletions
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qemu/target-mips/helper.c
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@ -386,6 +386,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
((address >> 9) & 0x007ffff0);
env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) |
(env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) |
(address & (TARGET_PAGE_MASK << 1));
#if defined(TARGET_MIPS64)
env->CP0_EntryHi &= env->SEGMask;