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https://github.com/yuzu-emu/unicorn.git
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tcg: Hoist max_insns computation to tb_gen_code
In order to handle TB's that translate to too much code, we need to place the control of the length of the translation in the hands of the code gen master loop. Backports commit 8b86d6d25807e13a63ab6ea879f976b9f18cc45a from qemu
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2479bbd3b2
commit
bca82cde84
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@ -1325,16 +1325,26 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
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TranslationBlock *tb;
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tb_page_addr_t phys_pc, phys_page2;
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tcg_insn_unit *gen_code_buf;
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int gen_code_size, search_size;
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int gen_code_size, search_size, max_insns;
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#ifdef CONFIG_PROFILER
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int64_t ti;
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#endif
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phys_pc = get_page_addr_code(env, pc);
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/* UNICORN: Commented out
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if (use_icount) {
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cflags |= CF_USE_ICOUNT;
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}*/
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/* Instruction counting */
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max_insns = cflags & CF_COUNT_MASK;
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if (max_insns == 0) {
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max_insns = CF_COUNT_MASK;
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}
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if (max_insns > TCG_MAX_INSNS) {
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max_insns = TCG_MAX_INSNS;
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}
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// Unicorn: commented out
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if (cpu->singlestep_enabled /*|| singlestep*/) {
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max_insns = 1;
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}
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tb = tb_alloc(env->uc, pc);
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if (unlikely(!tb)) {
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buffer_overflow:
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@ -1360,7 +1370,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
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tcg_func_start(tcg_ctx);
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tcg_ctx->cpu = ENV_GET_CPU(env);
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gen_intermediate_code(cpu, tb);
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gen_intermediate_code(cpu, tb, max_insns);
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tcg_ctx->cpu = NULL;
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// Unicorn: FIXME: Needs to be amended to work with new TCG
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@ -30,7 +30,7 @@ void translator_loop_temp_check(DisasContextBase *db)
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}
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void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
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CPUState *cpu, TranslationBlock *tb)
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CPUState *cpu, TranslationBlock *tb, int max_insns)
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{
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int bp_insn = 0;
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TCGContext *tcg_ctx = cpu->uc->tcg_ctx;
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@ -41,24 +41,12 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
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db->pc_next = db->pc_first;
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db->is_jmp = DISAS_NEXT;
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db->num_insns = 0;
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db->max_insns = max_insns;
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db->singlestep_enabled = cpu->singlestep_enabled;
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db->uc = cpu->uc;
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db->uc->block_full = false;
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/* Instruction counting */
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db->max_insns = tb_cflags(db->tb) & CF_COUNT_MASK;
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if (db->max_insns == 0) {
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db->max_insns = CF_COUNT_MASK;
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}
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if (db->max_insns > TCG_MAX_INSNS) {
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db->max_insns = TCG_MAX_INSNS;
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}
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// Unicorn: commented out
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if (db->singlestep_enabled /*|| singlestep*/) {
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db->max_insns = 1;
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}
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ops->init_disas_context(db, cpu);
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tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */
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@ -39,7 +39,7 @@ typedef ram_addr_t tb_page_addr_t;
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#include "qemu/log.h"
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void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb);
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void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns);
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void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
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target_ulong *data);
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@ -126,6 +126,7 @@ typedef struct TranslatorOps {
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* @db: Disassembly context.
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* @cpu: Target vCPU.
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* @tb: Translation block.
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* @max_insns: Maximum number of insns to translate.
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*
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* Generic translator loop.
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*
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@ -140,7 +141,7 @@ typedef struct TranslatorOps {
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* - When too many instructions have been translated.
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*/
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void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
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CPUState *cpu, TranslationBlock *tb);
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CPUState *cpu, TranslationBlock *tb, int max_insns);
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void translator_loop_temp_check(DisasContextBase *db);
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@ -13959,7 +13959,7 @@ static const TranslatorOps thumb_translator_ops = {
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};
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/* generate intermediate code for basic block 'tb'. */
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void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
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void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
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{
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DisasContext dc;
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const TranslatorOps *ops = &arm_translator_ops;
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@ -13973,7 +13973,7 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
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}
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#endif
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translator_loop(ops, &dc.base, cpu, tb);
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translator_loop(ops, &dc.base, cpu, tb, max_insns);
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}
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#if 0
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@ -9241,11 +9241,11 @@ static const TranslatorOps i386_tr_ops = {
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};
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/* generate intermediate code for basic block 'tb'. */
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void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
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void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
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{
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DisasContext dc;
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translator_loop(&i386_tr_ops, &dc.base, cpu, tb);
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translator_loop(&i386_tr_ops, &dc.base, cpu, tb, max_insns);
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}
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void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb,
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@ -6424,10 +6424,10 @@ static const TranslatorOps m68k_tr_ops = {
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m68k_tr_disas_log,
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};
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void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
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void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
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{
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DisasContext dc;
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translator_loop(&m68k_tr_ops, &dc.base, cpu, tb);
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translator_loop(&m68k_tr_ops, &dc.base, cpu, tb, max_insns);
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}
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void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb,
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@ -29920,11 +29920,11 @@ static const TranslatorOps mips_tr_ops = {
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mips_tr_disas_log,
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};
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void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
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void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb, int max_insns)
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{
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DisasContext ctx;
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translator_loop(&mips_tr_ops, &ctx.base, cs, tb);
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translator_loop(&mips_tr_ops, &ctx.base, cs, tb, max_insns);
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}
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#if 0
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@ -822,11 +822,11 @@ static const TranslatorOps riscv_tr_ops = {
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.disas_log = riscv_tr_disas_log,
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};
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void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
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void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
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{
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DisasContext ctx;
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translator_loop(&riscv_tr_ops, &ctx.base, cs, tb);
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translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns);
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}
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void riscv_translate_init(struct uc_struct *uc)
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@ -6048,11 +6048,11 @@ static const TranslatorOps sparc_tr_ops = {
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sparc_tr_disas_log,
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};
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void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
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void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
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{
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DisasContext dc = {{0}};
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translator_loop(&sparc_tr_ops, &dc.base, cs, tb);
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translator_loop(&sparc_tr_ops, &dc.base, cs, tb, max_insns);
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}
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void sparc_tcg_init(struct uc_struct *uc)
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