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target/arm: Implement FMOV (general) for fp16
Adding the fp16 moves to/from general registers. Backports commit 68130236e30a1ec64363f4915349feee181bfbc1 from qemu
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@ -5802,6 +5802,15 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
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tcg_gen_st_i64(tcg_ctx, tcg_rn, tcg_ctx->cpu_env, fp_reg_hi_offset(s, rd));
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tcg_gen_st_i64(tcg_ctx, tcg_rn, tcg_ctx->cpu_env, fp_reg_hi_offset(s, rd));
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clear_vec_high(s, true, rd);
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clear_vec_high(s, true, rd);
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break;
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break;
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case 3:
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/* 16 bit */
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tmp = tcg_temp_new_i64(tcg_ctx);
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tcg_gen_ext16u_i64(tcg_ctx, tmp, tcg_rn);
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write_fp_dreg(s, rd, tmp);
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tcg_temp_free_i64(tcg_ctx, tmp);
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break;
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default:
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g_assert_not_reached();
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}
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}
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} else {
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} else {
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TCGv_i64 tcg_rd = cpu_reg(s, rd);
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TCGv_i64 tcg_rd = cpu_reg(s, rd);
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@ -5819,6 +5828,12 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
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/* 64 bits from top half */
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/* 64 bits from top half */
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tcg_gen_ld_i64(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, fp_reg_hi_offset(s, rn));
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tcg_gen_ld_i64(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, fp_reg_hi_offset(s, rn));
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break;
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break;
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case 3:
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/* 16 bit */
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tcg_gen_ld16u_i64(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, fp_reg_offset(s, rn, MO_16));
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break;
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default:
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g_assert_not_reached();
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}
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}
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}
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}
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}
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}
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@ -5858,6 +5873,12 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
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case 0xa: /* 64 bit */
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case 0xa: /* 64 bit */
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case 0xd: /* 64 bit to top half of quad */
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case 0xd: /* 64 bit to top half of quad */
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break;
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break;
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case 0x6: /* 16-bit float, 32-bit int */
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case 0xe: /* 16-bit float, 64-bit int */
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if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
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break;
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}
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/* fallthru */
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default:
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default:
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/* all other sf/type/rmode combinations are invalid */
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/* all other sf/type/rmode combinations are invalid */
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unallocated_encoding(s);
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unallocated_encoding(s);
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