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target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU

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Backports commit a9a4181bdbf9eea81d718894bda607bd01b00f5b from qemu
This commit is contained in:
Craig Janeczek 2018-11-11 07:21:39 -05:00 committed by Lioncash
parent 97b7155db1
commit bd75529f43
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 95 additions and 7 deletions
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102
qemu/target/mips/translate.c
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@ -24481,6 +24481,100 @@ static void gen_mxu_d16mac(DisasContext *ctx)
tcg_temp_free(tcg_ctx, t3);
}
/*
* Q8MUL XRa, XRb, XRc, XRd - Parallel unsigned 8 bit pattern multiply
* Q8MULSU XRa, XRb, XRc, XRd - Parallel signed 8 bit pattern multiply
*/
static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0, t1, t2, t3, t4, t5, t6, t7;
TCGLabel *l0;
uint32_t XRa, XRb, XRc, XRd, sel;
t0 = tcg_temp_new(tcg_ctx);
t1 = tcg_temp_new(tcg_ctx);
t2 = tcg_temp_new(tcg_ctx);
t3 = tcg_temp_new(tcg_ctx);
t4 = tcg_temp_new(tcg_ctx);
t5 = tcg_temp_new(tcg_ctx);
t6 = tcg_temp_new(tcg_ctx);
t7 = tcg_temp_new(tcg_ctx);
l0 = gen_new_label(tcg_ctx);
XRa = extract32(ctx->opcode, 6, 4);
XRb = extract32(ctx->opcode, 10, 4);
XRc = extract32(ctx->opcode, 14, 4);
XRd = extract32(ctx->opcode, 18, 4);
sel = extract32(ctx->opcode, 22, 2);
gen_load_mxu_cr(ctx, t0);
tcg_gen_andi_tl(tcg_ctx, t0, t0, MXU_CR_MXU_EN);
tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_NE, t0, MXU_CR_MXU_EN, l0);
gen_load_mxu_gpr(ctx, t3, XRb);
gen_load_mxu_gpr(ctx, t7, XRc);
if (sel == 0x2) {
/* Q8MULSU */
tcg_gen_ext8s_tl(tcg_ctx, t0, t3);
tcg_gen_shri_tl(tcg_ctx, t3, t3, 8);
tcg_gen_ext8s_tl(tcg_ctx, t1, t3);
tcg_gen_shri_tl(tcg_ctx, t3, t3, 8);
tcg_gen_ext8s_tl(tcg_ctx, t2, t3);
tcg_gen_shri_tl(tcg_ctx, t3, t3, 8);
tcg_gen_ext8s_tl(tcg_ctx, t3, t3);
} else {
/* Q8MUL */
tcg_gen_ext8u_tl(tcg_ctx, t0, t3);
tcg_gen_shri_tl(tcg_ctx, t3, t3, 8);
tcg_gen_ext8u_tl(tcg_ctx, t1, t3);
tcg_gen_shri_tl(tcg_ctx, t3, t3, 8);
tcg_gen_ext8u_tl(tcg_ctx, t2, t3);
tcg_gen_shri_tl(tcg_ctx, t3, t3, 8);
tcg_gen_ext8u_tl(tcg_ctx, t3, t3);
}
tcg_gen_ext8u_tl(tcg_ctx, t4, t7);
tcg_gen_shri_tl(tcg_ctx, t7, t7, 8);
tcg_gen_ext8u_tl(tcg_ctx, t5, t7);
tcg_gen_shri_tl(tcg_ctx, t7, t7, 8);
tcg_gen_ext8u_tl(tcg_ctx, t6, t7);
tcg_gen_shri_tl(tcg_ctx, t7, t7, 8);
tcg_gen_ext8u_tl(tcg_ctx, t7, t7);
tcg_gen_mul_tl(tcg_ctx, t0, t0, t4);
tcg_gen_mul_tl(tcg_ctx, t1, t1, t5);
tcg_gen_mul_tl(tcg_ctx, t2, t2, t6);
tcg_gen_mul_tl(tcg_ctx, t3, t3, t7);
tcg_gen_andi_tl(tcg_ctx, t0, t0, 0xFFFF);
tcg_gen_andi_tl(tcg_ctx, t1, t1, 0xFFFF);
tcg_gen_andi_tl(tcg_ctx, t2, t2, 0xFFFF);
tcg_gen_andi_tl(tcg_ctx, t3, t3, 0xFFFF);
tcg_gen_shli_tl(tcg_ctx, t1, t1, 16);
tcg_gen_shli_tl(tcg_ctx, t3, t3, 16);
tcg_gen_or_tl(tcg_ctx, t0, t0, t1);
tcg_gen_or_tl(tcg_ctx, t1, t2, t3);
gen_store_mxu_gpr(ctx, t0, XRd);
gen_store_mxu_gpr(ctx, t1, XRa);
gen_set_label(tcg_ctx, l0);
tcg_temp_free(tcg_ctx, t0);
tcg_temp_free(tcg_ctx, t1);
tcg_temp_free(tcg_ctx, t2);
tcg_temp_free(tcg_ctx, t3);
tcg_temp_free(tcg_ctx, t4);
tcg_temp_free(tcg_ctx, t5);
tcg_temp_free(tcg_ctx, t6);
tcg_temp_free(tcg_ctx, t7);
}
/*
* Decoding engine for MXU
@ -25272,14 +25366,8 @@ static void decode_opc_mxu__pool18(CPUMIPSState *env, DisasContext *ctx)
switch (opcode) {
case OPC_MXU_Q8MUL:
/* TODO: Implement emulation of Q8MUL instruction. */
MIPS_INVAL("OPC_MXU_Q8MUL");
generate_exception_end(ctx, EXCP_RI);
break;
case OPC_MXU_Q8MULSU:
/* TODO: Implement emulation of Q8MULSU instruction. */
MIPS_INVAL("OPC_MXU_Q8MULSU");
generate_exception_end(ctx, EXCP_RI);
gen_mxu_q8mul_q8mulsu(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");