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target-i386: fix 32-bit addresses in LEA

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This was found with test-i386. The issue is that instructions
such as

addr32 lea (%eax), %rax

did not perform a 32-bit extension, because the LEA translation
skipped the gen_lea_v_seg step. That step does not just add
segments, it also takes care of extending from address size to
pointer size.

Backports commit 620abfb004543404bef1953e25da2ad77352941a from qemu
This commit is contained in:
Paolo Bonzini 2018-02-26 10:04:43 -05:00 committed by Lioncash
parent 8b239bd48b
commit be00a3e100
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 7 additions and 7 deletions
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10
qemu/target-i386/translate.c
View file

@ -547,14 +547,13 @@ static void gen_lea_v_seg(DisasContext *s, TCGMemOp aflag, TCGv a0,
#endif
case MO_32:
/* 32 bit address */
if (ovr_seg < 0) {
if (s->addseg) {
if (ovr_seg < 0 && s->addseg) {
ovr_seg = def_seg;
} else {
}
if (ovr_seg < 0) {
tcg_gen_ext32u_tl(tcg_ctx, cpu_A0, a0);
return;
}
}
break;
case MO_16:
/* 16 bit address */
@ -6032,7 +6031,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
{
AddressParts a = gen_lea_modrm_0(env, s, modrm);
TCGv ea = gen_lea_modrm_1(s, a);
gen_op_mov_reg_v(tcg_ctx, dflag, reg, ea);
gen_lea_v_seg(s, s->aflag, ea, -1, -1);
gen_op_mov_reg_v(tcg_ctx, dflag, reg, cpu_A0);
}
break;