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target/arm: Recover 4 bits from TBFLAGs
We had completely run out of TBFLAG bits. Split A- and M-profile bits into two overlapping buckets. This results in 4 free bits. We used to initialize all of the a32 and m32 fields in DisasContext by assignment, in arm_tr_init_disas_context. Now we only initialize either the a32 or m32 by assignment, because the bits overlap in tbflags. So zero the entire structure in gen_intermediate_code. Backports commit 79cabf1f473ca6e9fa0727f64ed9c2a84a36f0aa from qemu
This commit is contained in:
Richard Henderson
Lioncash
parent
153d7aadd5
commit
be3c71fb8b
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@ -3096,6 +3096,17 @@ typedef ARMCPU ArchCPU;
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* in 32 or 64 bit mode. The meaning of the other bits depends on that.
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* We put flags which are shared between 32 and 64 bit mode at the top
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* of the word, and flags which apply to only one mode at the bottom.
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*
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* 31 21 18 14 9 0
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* +--------------+-----+-----+----------+--------------+
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* | | | TBFLAG_A32 | |
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* | | +-----+----------+ TBFLAG_AM32 |
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* | TBFLAG_ANY | |TBFLAG_M32| |
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* | | +-------------------------|
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* | | | TBFLAG_A64 |
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* +--------------+-----------+-------------------------+
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* 31 21 14 0
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*
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*/
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FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1)
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FIELD(TBFLAG_ANY, MMUIDX, 28, 3)
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@ -3104,45 +3115,53 @@ FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1)
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/* Target EL if we take a floating-point-disabled exception */
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FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2)
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FIELD(TBFLAG_ANY, BE_DATA, 23, 1)
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/*
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* For A-profile only, target EL for debug exceptions.
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* Note that this overlaps with the M-profile-only HANDLER and STACKCHECK bits.
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*/
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/* For A-profile only, target EL for debug exceptions. */
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FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2)
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/* Bit usage when in AArch32 state: */
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FIELD(TBFLAG_A32, THUMB, 0, 1)
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FIELD(TBFLAG_A32, VECLEN, 1, 3)
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FIELD(TBFLAG_A32, VECSTRIDE, 4, 2)
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/*
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* Bit usage when in AArch32 state, both A- and M-profile.
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*/
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FIELD(TBFLAG_AM32, CONDEXEC, 0, 8) /* Not cached. */
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FIELD(TBFLAG_AM32, THUMB, 8, 1) /* Not cached. */
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/*
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* Bit usage when in AArch32 state, for A-profile only.
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*/
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FIELD(TBFLAG_A32, VECLEN, 9, 3) /* Not cached. */
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FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */
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/*
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* We store the bottom two bits of the CPAR as TB flags and handle
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* checks on the other bits at runtime. This shares the same bits as
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* VECSTRIDE, which is OK as no XScale CPU has VFP.
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*/
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FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2)
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FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2)
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FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. */
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FIELD(TBFLAG_A32, SCTLR_B, 15, 1)
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FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1)
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/*
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* Indicates whether cp register reads and writes by guest code should access
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* the secure or nonsecure bank of banked registers; note that this is not
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* the same thing as the current security state of the processor!
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*/
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FIELD(TBFLAG_A32, NS, 6, 1)
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FIELD(TBFLAG_A32, VFPEN, 7, 1)
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FIELD(TBFLAG_A32, CONDEXEC, 8, 8)
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FIELD(TBFLAG_A32, SCTLR_B, 16, 1)
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FIELD(TBFLAG_A32, HSTR_ACTIVE, 17, 1)
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FIELD(TBFLAG_A32, NS, 17, 1)
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/* For M profile only, set if FPCCR.LSPACT is set */
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FIELD(TBFLAG_A32, LSPACT, 18, 1)
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/* For M profile only, set if we must create a new FP context */
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FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1)
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/* For M profile only, set if FPCCR.S does not match current security state */
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FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1)
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/* For M profile only, Handler (ie not Thread) mode */
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FIELD(TBFLAG_A32, HANDLER, 21, 1)
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/* For M profile only, whether we should generate stack-limit checks */
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FIELD(TBFLAG_A32, STACKCHECK, 22, 1)
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/*
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* Bit usage when in AArch32 state, for M-profile only.
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*/
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/* Handler (ie not Thread) mode */
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FIELD(TBFLAG_M32, HANDLER, 9, 1)
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/* Whether we should generate stack-limit checks */
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FIELD(TBFLAG_M32, STACKCHECK, 10, 1)
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/* Set if FPCCR.LSPACT is set */
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FIELD(TBFLAG_M32, LSPACT, 11, 1) /* Not cached. */
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/* Set if we must create a new FP context */
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FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 12, 1) /* Not cached. */
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/* Set if FPCCR.S does not match current security state */
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FIELD(TBFLAG_M32, FPCCR_S_WRONG, 13, 1) /* Not cached. */
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/* Bit usage when in AArch64 state */
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/*
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* Bit usage when in AArch64 state
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*/
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FIELD(TBFLAG_A64, TBII, 0, 2)
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FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
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FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
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@ -11263,10 +11263,10 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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}
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} else {
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*pc = env->regs[15];
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flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb);
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flags = FIELD_DP32(flags, TBFLAG_AM32, THUMB, env->thumb);
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flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len);
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flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride);
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flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits);
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flags = FIELD_DP32(flags, TBFLAG_AM32, CONDEXEC, env->condexec_bits);
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flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env));
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flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env));
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if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)
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@ -11314,7 +11314,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el);
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if (arm_v7m_is_handler_mode(env)) {
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flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1);
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flags = FIELD_DP32(flags, TBFLAG_M32, HANDLER, 1);
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}
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/*
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@ -11325,12 +11325,12 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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arm_feature(env, ARM_FEATURE_M) &&
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!((mmu_idx & ARM_MMU_IDX_M_NEGPRI) &&
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(env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) {
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flags = FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1);
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flags = FIELD_DP32(flags, TBFLAG_M32, STACKCHECK, 1);
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}
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if (arm_feature(env, ARM_FEATURE_M_SECURITY) &&
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FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) != env->v7m.secure) {
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flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1);
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flags = FIELD_DP32(flags, TBFLAG_M32, FPCCR_S_WRONG, 1);
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}
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if (arm_feature(env, ARM_FEATURE_M) &&
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@ -11343,14 +11343,14 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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* FP context; we must create a new FP context before executing
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* any FP insn.
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*/
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flags = FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED, 1);
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flags = FIELD_DP32(flags, TBFLAG_M32, NEW_FP_CTXT_NEEDED, 1);
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}
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if (arm_feature(env, ARM_FEATURE_M)) {
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bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK;
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if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) {
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flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1);
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flags = FIELD_DP32(flags, TBFLAG_M32, LSPACT, 1);
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}
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}
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@ -11160,38 +11160,48 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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*/
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dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) &&
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!arm_el_is_aa64(env, 3);
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dc->thumb = FIELD_EX32(tb_flags, TBFLAG_A32, THUMB);
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dc->sctlr_b = FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR_B);
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dc->hstr_active = FIELD_EX32(tb_flags, TBFLAG_A32, HSTR_ACTIVE);
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dc->thumb = FIELD_EX32(tb_flags, TBFLAG_AM32, THUMB);
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dc->be_data = FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE;
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condexec = FIELD_EX32(tb_flags, TBFLAG_A32, CONDEXEC);
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condexec = FIELD_EX32(tb_flags, TBFLAG_AM32, CONDEXEC);
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dc->condexec_mask = (condexec & 0xf) << 1;
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dc->condexec_cond = condexec >> 4;
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core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX);
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dc->mmu_idx = core_to_arm_mmu_idx(env, core_mmu_idx);
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dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx);
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#if !defined(CONFIG_USER_ONLY)
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dc->user = (dc->current_el == 0);
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#endif
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dc->ns = FIELD_EX32(tb_flags, TBFLAG_A32, NS);
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dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL);
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dc->vfp_enabled = FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN);
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dc->vec_len = FIELD_EX32(tb_flags, TBFLAG_A32, VECLEN);
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if (arm_feature(env, ARM_FEATURE_XSCALE)) {
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dc->c15_cpar = FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR);
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dc->vec_stride = 0;
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if (arm_feature(env, ARM_FEATURE_M)) {
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dc->vfp_enabled = 1;
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dc->be_data = MO_TE;
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dc->v7m_handler_mode = FIELD_EX32(tb_flags, TBFLAG_M32, HANDLER);
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dc->v8m_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) &&
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regime_is_secure(env, dc->mmu_idx);
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dc->v8m_stackcheck = FIELD_EX32(tb_flags, TBFLAG_M32, STACKCHECK);
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dc->v8m_fpccr_s_wrong =
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FIELD_EX32(tb_flags, TBFLAG_M32, FPCCR_S_WRONG);
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dc->v7m_new_fp_ctxt_needed =
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FIELD_EX32(tb_flags, TBFLAG_M32, NEW_FP_CTXT_NEEDED);
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dc->v7m_lspact = FIELD_EX32(tb_flags, TBFLAG_M32, LSPACT);
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} else {
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dc->vec_stride = FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE);
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dc->c15_cpar = 0;
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dc->be_data =
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FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE;
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dc->debug_target_el =
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FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL);
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dc->sctlr_b = FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR_B);
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dc->hstr_active = FIELD_EX32(tb_flags, TBFLAG_A32, HSTR_ACTIVE);
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dc->ns = FIELD_EX32(tb_flags, TBFLAG_A32, NS);
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dc->vfp_enabled = FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN);
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if (arm_feature(env, ARM_FEATURE_XSCALE)) {
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dc->c15_cpar = FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR);
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} else {
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dc->vec_len = FIELD_EX32(tb_flags, TBFLAG_A32, VECLEN);
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dc->vec_stride = FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE);
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}
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}
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dc->v7m_handler_mode = FIELD_EX32(tb_flags, TBFLAG_A32, HANDLER);
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dc->v8m_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) &&
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regime_is_secure(env, dc->mmu_idx);
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dc->v8m_stackcheck = FIELD_EX32(tb_flags, TBFLAG_A32, STACKCHECK);
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dc->v8m_fpccr_s_wrong = FIELD_EX32(tb_flags, TBFLAG_A32, FPCCR_S_WRONG);
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dc->v7m_new_fp_ctxt_needed =
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FIELD_EX32(tb_flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED);
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dc->v7m_lspact = FIELD_EX32(tb_flags, TBFLAG_A32, LSPACT);
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dc->cp_regs = cpu->cp_regs;
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dc->features = env->features;
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@ -11213,9 +11223,6 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE);
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dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS);
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dc->is_ldex = false;
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if (!arm_feature(env, ARM_FEATURE_M)) {
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dc->debug_target_el = FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL);
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}
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dc->page_start = dc->base.pc_first & TARGET_PAGE_MASK;
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@ -11676,10 +11683,10 @@ static const TranslatorOps thumb_translator_ops = {
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/* generate intermediate code for basic block 'tb'. */
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void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
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{
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DisasContext dc;
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DisasContext dc = {};
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const TranslatorOps *ops = &arm_translator_ops;
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if (FIELD_EX32(tb->flags, TBFLAG_A32, THUMB)) {
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if (FIELD_EX32(tb->flags, TBFLAG_AM32, THUMB)) {
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ops = &thumb_translator_ops;
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}
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#ifdef TARGET_AARCH64
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