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target/arm: Implement SVE scatter store vector immediate

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Backports commit 408ecde97bd30f8ec13f831976d0a9a6535bb569 from qemu
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Richard Henderson 2018-07-03 03:09:49 -04:00 committed by Lioncash
parent 892a9a66eb
commit be65f60799
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 72 additions and 26 deletions
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11
qemu/target/arm/sve.decode
View file

@ -83,6 +83,7 @@
&rprr_gather_load rd pg rn rm esz msz u ff xs scale
&rpri_gather_load rd pg rn imm esz msz u ff
&rprr_scatter_store rd pg rn rm esz msz xs scale
&rpri_scatter_store rd pg rn imm esz msz
###########################################################################
# Named instruction formats. These are generally used to
@ -219,6 +220,8 @@
&rprr_store nreg=0
@rprr_scatter_store ....... msz:2 .. rm:5 ... pg:3 rn:5 rd:5 \
&rprr_scatter_store
@rpri_scatter_store ....... msz:2 .. imm:5 ... pg:3 rn:5 rd:5 \
&rpri_scatter_store
###########################################################################
# Instruction patterns. Grouped according to the SVE encodingindex.xhtml.
@ -932,6 +935,14 @@ ST1_zprz 1110010 .. 01 ..... 101 ... ..... ..... \
ST1_zprz 1110010 .. 00 ..... 101 ... ..... ..... \
@rprr_scatter_store xs=2 esz=3 scale=0
# SVE 64-bit scatter store (vector plus immediate)
ST1_zpiz 1110010 .. 10 ..... 101 ... ..... ..... \
@rpri_scatter_store esz=3
# SVE 32-bit scatter store (vector plus immediate)
ST1_zpiz 1110010 .. 11 ..... 101 ... ..... ..... \
@rpri_scatter_store esz=2
# SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offset)
# Require msz > 0
ST1_zprz 1110010 .. 01 ..... 100 ... ..... ..... \

87
qemu/target/arm/translate-sve.c
View file

@ -4555,32 +4555,34 @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a, uint32_t insn)
return true;
}
/* Indexed by [xs][msz]. */
static gen_helper_gvec_mem_scatter * const scatter_store_fn32[2][3] = {
{ gen_helper_sve_stbs_zsu,
gen_helper_sve_sths_zsu,
gen_helper_sve_stss_zsu, },
{ gen_helper_sve_stbs_zss,
gen_helper_sve_sths_zss,
gen_helper_sve_stss_zss, },
};
/* Note that we overload xs=2 to indicate 64-bit offset. */
static gen_helper_gvec_mem_scatter * const scatter_store_fn64[3][4] = {
{ gen_helper_sve_stbd_zsu,
gen_helper_sve_sthd_zsu,
gen_helper_sve_stsd_zsu,
gen_helper_sve_stdd_zsu, },
{ gen_helper_sve_stbd_zss,
gen_helper_sve_sthd_zss,
gen_helper_sve_stsd_zss,
gen_helper_sve_stdd_zss, },
{ gen_helper_sve_stbd_zd,
gen_helper_sve_sthd_zd,
gen_helper_sve_stsd_zd,
gen_helper_sve_stdd_zd, },
};
static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a, uint32_t insn)
{
/* Indexed by [xs][msz]. */
static gen_helper_gvec_mem_scatter * const fn32[2][3] = {
{ gen_helper_sve_stbs_zsu,
gen_helper_sve_sths_zsu,
gen_helper_sve_stss_zsu, },
{ gen_helper_sve_stbs_zss,
gen_helper_sve_sths_zss,
gen_helper_sve_stss_zss, },
};
/* Note that we overload xs=2 to indicate 64-bit offset. */
static gen_helper_gvec_mem_scatter * const fn64[3][4] = {
{ gen_helper_sve_stbd_zsu,
gen_helper_sve_sthd_zsu,
gen_helper_sve_stsd_zsu,
gen_helper_sve_stdd_zsu, },
{ gen_helper_sve_stbd_zss,
gen_helper_sve_sthd_zss,
gen_helper_sve_stsd_zss,
gen_helper_sve_stdd_zss, },
{ gen_helper_sve_stbd_zd,
gen_helper_sve_sthd_zd,
gen_helper_sve_stsd_zd,
gen_helper_sve_stdd_zd, },
};
gen_helper_gvec_mem_scatter *fn;
if (a->esz < a->msz || (a->msz == 0 && a->scale)) {
@ -4591,10 +4593,10 @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a, uint32_t insn)
}
switch (a->esz) {
case MO_32:
fn = fn32[a->xs][a->msz];
fn = scatter_store_fn32[a->xs][a->msz];
break;
case MO_64:
fn = fn64[a->xs][a->msz];
fn = scatter_store_fn64[a->xs][a->msz];
break;
default:
g_assert_not_reached();
@ -4604,6 +4606,39 @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1_zprz *a, uint32_t insn)
return true;
}
static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a, uint32_t insn)
{
gen_helper_gvec_mem_scatter *fn = NULL;
TCGv_i64 imm;
if (a->esz < a->msz) {
return false;
}
if (!sve_access_check(s)) {
return true;
}
TCGContext *tcg_ctx = s->uc->tcg_ctx;
switch (a->esz) {
case MO_32:
fn = scatter_store_fn32[0][a->msz];
break;
case MO_64:
fn = scatter_store_fn64[2][a->msz];
break;
}
assert(fn != NULL);
/* Treat ST1_zpiz (zn[x] + imm) the same way as ST1_zprz (rn + zm[x])
* by loading the immediate into the scalar parameter.
*/
imm = tcg_const_i64(tcg_ctx, a->imm << a->msz);
do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, fn);
tcg_temp_free_i64(tcg_ctx, imm);
return true;
}
/*
* Prefetches
*/