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target/arm: Convert Neon VSHL and VSLI 2-reg-shift insn to decodetree

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Convert the VSHL and VSLI insns from the Neon 2-registers-and-a-shift
group to decodetree.

Backports commit d3c8c736f8b4bdd02831076286b1788232f46ced from qemu
This commit is contained in:
Peter Maydell 2020-06-15 12:05:19 -04:00 committed by Lioncash
parent 1d95dd1c89
commit bf18bf983d
3 changed files with 72 additions and 10 deletions
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25
qemu/target/arm/neon-dp.decode
View file

@ -201,3 +201,28 @@ VRECPS_fp_3s 1111 001 0 0 . 0 . .... .... 1111 ... 1 .... @3same_fp
VRSQRTS_fp_3s 1111 001 0 0 . 1 . .... .... 1111 ... 1 .... @3same_fp VRSQRTS_fp_3s 1111 001 0 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
VMAXNM_fp_3s 1111 001 1 0 . 0 . .... .... 1111 ... 1 .... @3same_fp VMAXNM_fp_3s 1111 001 1 0 . 0 . .... .... 1111 ... 1 .... @3same_fp
VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1 .... @3same_fp
######################################################################
# 2-reg-and-shift grouping:
# 1111 001 U 1 D immH:3 immL:3 Vd:4 opc:4 L Q M 1 Vm:4
######################################################################
&2reg_shift vm vd q shift size
@2reg_shl_d .... ... . . . shift:6 .... .... 1 q:1 . . .... \
&2reg_shift vm=%vm_dp vd=%vd_dp size=3
@2reg_shl_s .... ... . . . 1 shift:5 .... .... 0 q:1 . . .... \
&2reg_shift vm=%vm_dp vd=%vd_dp size=2
@2reg_shl_h .... ... . . . 01 shift:4 .... .... 0 q:1 . . .... \
&2reg_shift vm=%vm_dp vd=%vd_dp size=1
@2reg_shl_b .... ... . . . 001 shift:3 .... .... 0 q:1 . . .... \
&2reg_shift vm=%vm_dp vd=%vd_dp size=0
VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
VSHL_2sh 1111 001 0 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b
VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b

39
qemu/target/arm/translate-neon.inc.c
View file

@ -1218,3 +1218,42 @@ static bool do_3same_fp_pair(DisasContext *s, arg_3same *a, VFPGen3OpSPFn *fn)
DO_3S_FP_PAIR(VPADD, gen_helper_vfp_adds) DO_3S_FP_PAIR(VPADD, gen_helper_vfp_adds)
DO_3S_FP_PAIR(VPMAX, gen_helper_vfp_maxs) DO_3S_FP_PAIR(VPMAX, gen_helper_vfp_maxs)
DO_3S_FP_PAIR(VPMIN, gen_helper_vfp_mins) DO_3S_FP_PAIR(VPMIN, gen_helper_vfp_mins)
static bool do_vector_2sh(DisasContext *s, arg_2reg_shift *a, GVecGen2iFn *fn)
{
/* Handle a 2-reg-shift insn which can be vectorized. */
TCGContext *tcg_ctx = s->uc->tcg_ctx;
int vec_size = a->q ? 16 : 8;
int rd_ofs = neon_reg_offset(a->vd, 0);
int rm_ofs = neon_reg_offset(a->vm, 0);
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
return false;
}
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) &&
((a->vd | a->vm) & 0x10)) {
return false;
}
if ((a->vm | a->vd) & a->q) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
fn(tcg_ctx, a->size, rd_ofs, rm_ofs, a->shift, vec_size, vec_size);
return true;
}
#define DO_2SH(INSN, FUNC) \
static bool trans_##INSN##_2sh(DisasContext *s, arg_2reg_shift *a) \
{ \
return do_vector_2sh(s, a, FUNC); \
} \
DO_2SH(VSHL, tcg_gen_gvec_shli)
DO_2SH(VSLI, gen_gvec_sli)

18
qemu/target/arm/translate.c
View file

@ -5443,6 +5443,14 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
if ((insn & 0x00380080) != 0) { if ((insn & 0x00380080) != 0) {
/* Two registers and shift. */ /* Two registers and shift. */
op = (insn >> 8) & 0xf; op = (insn >> 8) & 0xf;
switch (op) {
case 5: /* VSHL, VSLI */
return 1; /* handled by decodetree */
default:
break;
}
if (insn & (1 << 7)) { if (insn & (1 << 7)) {
/* 64-bit shift. */ /* 64-bit shift. */
if (op > 7) { if (op > 7) {
@ -5512,16 +5520,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
gen_gvec_sri(tcg_ctx, size, rd_ofs, rm_ofs, shift, gen_gvec_sri(tcg_ctx, size, rd_ofs, rm_ofs, shift,
vec_size, vec_size); vec_size, vec_size);
return 0; return 0;
case 5: /* VSHL, VSLI */
if (u) { /* VSLI */
gen_gvec_sli(tcg_ctx, size, rd_ofs, rm_ofs, shift,
vec_size, vec_size);
} else { /* VSHL */
tcg_gen_gvec_shli(tcg_ctx, size, rd_ofs, rm_ofs, shift,
vec_size, vec_size);
}
return 0;
} }
if (size == 3) { if (size == 3) {