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target/riscv: implementation-defined constant parameters

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vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.

Backports 32931383270e2ca8209267ca99f23f3c5f780982 from qemu
This commit is contained in:
LIU Zhiwei 2021-02-26 02:23:26 -05:00 committed by Lioncash
parent 0968caa249
commit bff31d8822
2 changed files with 12 additions and 1 deletions
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8
qemu/target/riscv/cpu.c
View file

@ -98,6 +98,11 @@ static void set_priv_version(CPURISCVState *env, int priv_ver)
env->priv_ver = priv_ver;
}
static void set_vext_version(CPURISCVState *env, int vext_ver)
{
env->vext_ver = vext_ver;
}
static void set_feature(CPURISCVState *env, int feature)
{
env->features |= (1ULL << feature);
@ -114,7 +119,8 @@ static void riscv_any_cpu_init(struct uc_struct *uc, Object *obj, void *opaque)
{
CPURISCVState *env = &RISCV_CPU(uc, obj)->env;
set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_11_0);
set_priv_version(env, PRIV_VERSION_1_11_0);
set_vext_version(env, VEXT_VERSION_0_07_1);
set_resetvec(env, DEFAULT_RSTVEC);
}

5
qemu/target/riscv/cpu.h
View file

@ -83,6 +83,8 @@ enum {
#define PRIV_VERSION_1_10_0 0x00011000
#define PRIV_VERSION_1_11_0 0x00011100
#define VEXT_VERSION_0_07_1 0x00000701
#define TRANSLATE_PMP_FAIL 2
#define TRANSLATE_FAIL 1
#define TRANSLATE_SUCCESS 0
@ -118,6 +120,7 @@ struct CPURISCVState {
target_ulong guest_phys_fault_addr;
target_ulong priv_ver;
target_ulong vext_ver;
target_ulong misa;
target_ulong misa_mask;
@ -279,6 +282,8 @@ typedef struct RISCVCPU {
struct {
bool ext_ifencei;
bool ext_icsr;
uint16_t vlen;
uint16_t elen;
} cfg;
} RISCVCPU;