target/arm: Convert PMULL.64 to gvec

The gvec form will be needed for implementing SVE2.

Backports commit b9ed510e46f2f9e31e5e8adb4661d5d1cbe9a459 from qemu

qemu/aarch64.h

@@ -1216,6 +1216,7 @@
 #define helper_gvec_orc helper_gvec_orc_aarch64
 #define helper_gvec_ors helper_gvec_ors_aarch64
 #define helper_gvec_pmul_b helper_gvec_pmul_b_aarch64
+#define helper_gvec_pmull_q helper_gvec_pmull_q_aarch64
 #define helper_gvec_qrdmlah_s16 helper_gvec_qrdmlah_s16_aarch64
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_aarch64
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_aarch64
@@ -1559,8 +1560,6 @@
 #define helper_neon_pmin_s8 helper_neon_pmin_s8_aarch64
 #define helper_neon_pmin_u16 helper_neon_pmin_u16_aarch64
 #define helper_neon_pmin_u8 helper_neon_pmin_u8_aarch64
-#define helper_neon_pmull_64_hi helper_neon_pmull_64_hi_aarch64
-#define helper_neon_pmull_64_lo helper_neon_pmull_64_lo_aarch64
 #define helper_neon_qabs_s16 helper_neon_qabs_s16_aarch64
 #define helper_neon_qabs_s32 helper_neon_qabs_s32_aarch64
 #define helper_neon_qabs_s64 helper_neon_qabs_s64_aarch64

qemu/aarch64eb.h

@@ -1216,6 +1216,7 @@
 #define helper_gvec_orc helper_gvec_orc_aarch64eb
 #define helper_gvec_ors helper_gvec_ors_aarch64eb
 #define helper_gvec_pmul_b helper_gvec_pmul_b_aarch64eb
+#define helper_gvec_pmull_q helper_gvec_pmull_q_aarch64eb
 #define helper_gvec_qrdmlah_s16 helper_gvec_qrdmlah_s16_aarch64eb
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_aarch64eb
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_aarch64eb
@@ -1559,8 +1560,6 @@
 #define helper_neon_pmin_s8 helper_neon_pmin_s8_aarch64eb
 #define helper_neon_pmin_u16 helper_neon_pmin_u16_aarch64eb
 #define helper_neon_pmin_u8 helper_neon_pmin_u8_aarch64eb
-#define helper_neon_pmull_64_hi helper_neon_pmull_64_hi_aarch64eb
-#define helper_neon_pmull_64_lo helper_neon_pmull_64_lo_aarch64eb
 #define helper_neon_qabs_s16 helper_neon_qabs_s16_aarch64eb
 #define helper_neon_qabs_s32 helper_neon_qabs_s32_aarch64eb
 #define helper_neon_qabs_s64 helper_neon_qabs_s64_aarch64eb

qemu/arm.h

@@ -1216,6 +1216,7 @@
 #define helper_gvec_orc helper_gvec_orc_arm
 #define helper_gvec_ors helper_gvec_ors_arm
 #define helper_gvec_pmul_b helper_gvec_pmul_b_arm
+#define helper_gvec_pmull_q helper_gvec_pmull_q_arm
 #define helper_gvec_qrdmlah_s16 helper_gvec_qrdmlah_s16_arm
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_arm
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_arm
@@ -1559,8 +1560,6 @@
 #define helper_neon_pmin_s8 helper_neon_pmin_s8_arm
 #define helper_neon_pmin_u16 helper_neon_pmin_u16_arm
 #define helper_neon_pmin_u8 helper_neon_pmin_u8_arm
-#define helper_neon_pmull_64_hi helper_neon_pmull_64_hi_arm
-#define helper_neon_pmull_64_lo helper_neon_pmull_64_lo_arm
 #define helper_neon_qabs_s16 helper_neon_qabs_s16_arm
 #define helper_neon_qabs_s32 helper_neon_qabs_s32_arm
 #define helper_neon_qabs_s64 helper_neon_qabs_s64_arm

qemu/armeb.h

@@ -1216,6 +1216,7 @@
 #define helper_gvec_orc helper_gvec_orc_armeb
 #define helper_gvec_ors helper_gvec_ors_armeb
 #define helper_gvec_pmul_b helper_gvec_pmul_b_armeb
+#define helper_gvec_pmull_q helper_gvec_pmull_q_armeb
 #define helper_gvec_qrdmlah_s16 helper_gvec_qrdmlah_s16_armeb
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_armeb
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_armeb
@@ -1559,8 +1560,6 @@
 #define helper_neon_pmin_s8 helper_neon_pmin_s8_armeb
 #define helper_neon_pmin_u16 helper_neon_pmin_u16_armeb
 #define helper_neon_pmin_u8 helper_neon_pmin_u8_armeb
-#define helper_neon_pmull_64_hi helper_neon_pmull_64_hi_armeb
-#define helper_neon_pmull_64_lo helper_neon_pmull_64_lo_armeb
 #define helper_neon_qabs_s16 helper_neon_qabs_s16_armeb
 #define helper_neon_qabs_s32 helper_neon_qabs_s32_armeb
 #define helper_neon_qabs_s64 helper_neon_qabs_s64_armeb

qemu/header_gen.py

@@ -1222,6 +1222,7 @@ symbols = (
     'helper_gvec_orc',
     'helper_gvec_ors',
     'helper_gvec_pmul_b',
+    'helper_gvec_pmull_q',
     'helper_gvec_qrdmlah_s16',
     'helper_gvec_qrdmlah_s32',
     'helper_gvec_qrdmlsh_s16',
@@ -1565,8 +1566,6 @@ symbols = (
     'helper_neon_pmin_s8',
     'helper_neon_pmin_u16',
     'helper_neon_pmin_u8',
-    'helper_neon_pmull_64_hi',
-    'helper_neon_pmull_64_lo',
     'helper_neon_qabs_s16',
     'helper_neon_qabs_s32',
     'helper_neon_qabs_s64',

qemu/m68k.h

@@ -1216,6 +1216,7 @@
 #define helper_gvec_orc helper_gvec_orc_m68k
 #define helper_gvec_ors helper_gvec_ors_m68k
 #define helper_gvec_pmul_b helper_gvec_pmul_b_m68k
+#define helper_gvec_pmull_q helper_gvec_pmull_q_m68k
 #define helper_gvec_qrdmlah_s16 helper_gvec_qrdmlah_s16_m68k
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_m68k
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_m68k
@@ -1559,8 +1560,6 @@
 #define helper_neon_pmin_s8 helper_neon_pmin_s8_m68k
 #define helper_neon_pmin_u16 helper_neon_pmin_u16_m68k
 #define helper_neon_pmin_u8 helper_neon_pmin_u8_m68k
-#define helper_neon_pmull_64_hi helper_neon_pmull_64_hi_m68k
-#define helper_neon_pmull_64_lo helper_neon_pmull_64_lo_m68k
 #define helper_neon_qabs_s16 helper_neon_qabs_s16_m68k
 #define helper_neon_qabs_s32 helper_neon_qabs_s32_m68k
 #define helper_neon_qabs_s64 helper_neon_qabs_s64_m68k

qemu/mips.h

@@ -1216,6 +1216,7 @@
 #define helper_gvec_orc helper_gvec_orc_mips
 #define helper_gvec_ors helper_gvec_ors_mips
 #define helper_gvec_pmul_b helper_gvec_pmul_b_mips
+#define helper_gvec_pmull_q helper_gvec_pmull_q_mips
 #define helper_gvec_qrdmlah_s16 helper_gvec_qrdmlah_s16_mips
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_mips
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_mips
@@ -1559,8 +1560,6 @@
 #define helper_neon_pmin_s8 helper_neon_pmin_s8_mips
 #define helper_neon_pmin_u16 helper_neon_pmin_u16_mips
 #define helper_neon_pmin_u8 helper_neon_pmin_u8_mips
-#define helper_neon_pmull_64_hi helper_neon_pmull_64_hi_mips
-#define helper_neon_pmull_64_lo helper_neon_pmull_64_lo_mips
 #define helper_neon_qabs_s16 helper_neon_qabs_s16_mips
 #define helper_neon_qabs_s32 helper_neon_qabs_s32_mips
 #define helper_neon_qabs_s64 helper_neon_qabs_s64_mips

qemu/mips64.h

@@ -1216,6 +1216,7 @@
 #define helper_gvec_orc helper_gvec_orc_mips64
 #define helper_gvec_ors helper_gvec_ors_mips64
 #define helper_gvec_pmul_b helper_gvec_pmul_b_mips64
+#define helper_gvec_pmull_q helper_gvec_pmull_q_mips64
 #define helper_gvec_qrdmlah_s16 helper_gvec_qrdmlah_s16_mips64
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_mips64
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_mips64
@@ -1559,8 +1560,6 @@
 #define helper_neon_pmin_s8 helper_neon_pmin_s8_mips64
 #define helper_neon_pmin_u16 helper_neon_pmin_u16_mips64
 #define helper_neon_pmin_u8 helper_neon_pmin_u8_mips64
-#define helper_neon_pmull_64_hi helper_neon_pmull_64_hi_mips64
-#define helper_neon_pmull_64_lo helper_neon_pmull_64_lo_mips64
 #define helper_neon_qabs_s16 helper_neon_qabs_s16_mips64
 #define helper_neon_qabs_s32 helper_neon_qabs_s32_mips64
 #define helper_neon_qabs_s64 helper_neon_qabs_s64_mips64

qemu/mips64el.h

@@ -1216,6 +1216,7 @@
 #define helper_gvec_orc helper_gvec_orc_mips64el
 #define helper_gvec_ors helper_gvec_ors_mips64el
 #define helper_gvec_pmul_b helper_gvec_pmul_b_mips64el
+#define helper_gvec_pmull_q helper_gvec_pmull_q_mips64el
 #define helper_gvec_qrdmlah_s16 helper_gvec_qrdmlah_s16_mips64el
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_mips64el
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_mips64el
@@ -1559,8 +1560,6 @@
 #define helper_neon_pmin_s8 helper_neon_pmin_s8_mips64el
 #define helper_neon_pmin_u16 helper_neon_pmin_u16_mips64el
 #define helper_neon_pmin_u8 helper_neon_pmin_u8_mips64el
-#define helper_neon_pmull_64_hi helper_neon_pmull_64_hi_mips64el
-#define helper_neon_pmull_64_lo helper_neon_pmull_64_lo_mips64el
 #define helper_neon_qabs_s16 helper_neon_qabs_s16_mips64el
 #define helper_neon_qabs_s32 helper_neon_qabs_s32_mips64el
 #define helper_neon_qabs_s64 helper_neon_qabs_s64_mips64el

qemu/mipsel.h

@@ -1216,6 +1216,7 @@
 #define helper_gvec_orc helper_gvec_orc_mipsel
 #define helper_gvec_ors helper_gvec_ors_mipsel
 #define helper_gvec_pmul_b helper_gvec_pmul_b_mipsel
+#define helper_gvec_pmull_q helper_gvec_pmull_q_mipsel
 #define helper_gvec_qrdmlah_s16 helper_gvec_qrdmlah_s16_mipsel
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_mipsel
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_mipsel
@@ -1559,8 +1560,6 @@
 #define helper_neon_pmin_s8 helper_neon_pmin_s8_mipsel
 #define helper_neon_pmin_u16 helper_neon_pmin_u16_mipsel
 #define helper_neon_pmin_u8 helper_neon_pmin_u8_mipsel
-#define helper_neon_pmull_64_hi helper_neon_pmull_64_hi_mipsel
-#define helper_neon_pmull_64_lo helper_neon_pmull_64_lo_mipsel
 #define helper_neon_qabs_s16 helper_neon_qabs_s16_mipsel
 #define helper_neon_qabs_s32 helper_neon_qabs_s32_mipsel
 #define helper_neon_qabs_s64 helper_neon_qabs_s64_mipsel

qemu/powerpc.h

@@ -1216,6 +1216,7 @@
 #define helper_gvec_orc helper_gvec_orc_powerpc
 #define helper_gvec_ors helper_gvec_ors_powerpc
 #define helper_gvec_pmul_b helper_gvec_pmul_b_powerpc
+#define helper_gvec_pmull_q helper_gvec_pmull_q_powerpc
 #define helper_gvec_qrdmlah_s16 helper_gvec_qrdmlah_s16_powerpc
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_powerpc
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_powerpc
@@ -1559,8 +1560,6 @@
 #define helper_neon_pmin_s8 helper_neon_pmin_s8_powerpc
 #define helper_neon_pmin_u16 helper_neon_pmin_u16_powerpc
 #define helper_neon_pmin_u8 helper_neon_pmin_u8_powerpc
-#define helper_neon_pmull_64_hi helper_neon_pmull_64_hi_powerpc
-#define helper_neon_pmull_64_lo helper_neon_pmull_64_lo_powerpc
 #define helper_neon_qabs_s16 helper_neon_qabs_s16_powerpc
 #define helper_neon_qabs_s32 helper_neon_qabs_s32_powerpc
 #define helper_neon_qabs_s64 helper_neon_qabs_s64_powerpc

qemu/riscv32.h

@@ -1216,6 +1216,7 @@
 #define helper_gvec_orc helper_gvec_orc_riscv32
 #define helper_gvec_ors helper_gvec_ors_riscv32
 #define helper_gvec_pmul_b helper_gvec_pmul_b_riscv32
+#define helper_gvec_pmull_q helper_gvec_pmull_q_riscv32
 #define helper_gvec_qrdmlah_s16 helper_gvec_qrdmlah_s16_riscv32
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_riscv32
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_riscv32
@@ -1559,8 +1560,6 @@
 #define helper_neon_pmin_s8 helper_neon_pmin_s8_riscv32
 #define helper_neon_pmin_u16 helper_neon_pmin_u16_riscv32
 #define helper_neon_pmin_u8 helper_neon_pmin_u8_riscv32
-#define helper_neon_pmull_64_hi helper_neon_pmull_64_hi_riscv32
-#define helper_neon_pmull_64_lo helper_neon_pmull_64_lo_riscv32
 #define helper_neon_qabs_s16 helper_neon_qabs_s16_riscv32
 #define helper_neon_qabs_s32 helper_neon_qabs_s32_riscv32
 #define helper_neon_qabs_s64 helper_neon_qabs_s64_riscv32

qemu/riscv64.h

@@ -1216,6 +1216,7 @@
 #define helper_gvec_orc helper_gvec_orc_riscv64
 #define helper_gvec_ors helper_gvec_ors_riscv64
 #define helper_gvec_pmul_b helper_gvec_pmul_b_riscv64
+#define helper_gvec_pmull_q helper_gvec_pmull_q_riscv64
 #define helper_gvec_qrdmlah_s16 helper_gvec_qrdmlah_s16_riscv64
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_riscv64
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_riscv64
@@ -1559,8 +1560,6 @@
 #define helper_neon_pmin_s8 helper_neon_pmin_s8_riscv64
 #define helper_neon_pmin_u16 helper_neon_pmin_u16_riscv64
 #define helper_neon_pmin_u8 helper_neon_pmin_u8_riscv64
-#define helper_neon_pmull_64_hi helper_neon_pmull_64_hi_riscv64
-#define helper_neon_pmull_64_lo helper_neon_pmull_64_lo_riscv64
 #define helper_neon_qabs_s16 helper_neon_qabs_s16_riscv64
 #define helper_neon_qabs_s32 helper_neon_qabs_s32_riscv64
 #define helper_neon_qabs_s64 helper_neon_qabs_s64_riscv64

qemu/sparc.h

@@ -1216,6 +1216,7 @@
 #define helper_gvec_orc helper_gvec_orc_sparc
 #define helper_gvec_ors helper_gvec_ors_sparc
 #define helper_gvec_pmul_b helper_gvec_pmul_b_sparc
+#define helper_gvec_pmull_q helper_gvec_pmull_q_sparc
 #define helper_gvec_qrdmlah_s16 helper_gvec_qrdmlah_s16_sparc
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_sparc
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_sparc
@@ -1559,8 +1560,6 @@
 #define helper_neon_pmin_s8 helper_neon_pmin_s8_sparc
 #define helper_neon_pmin_u16 helper_neon_pmin_u16_sparc
 #define helper_neon_pmin_u8 helper_neon_pmin_u8_sparc
-#define helper_neon_pmull_64_hi helper_neon_pmull_64_hi_sparc
-#define helper_neon_pmull_64_lo helper_neon_pmull_64_lo_sparc
 #define helper_neon_qabs_s16 helper_neon_qabs_s16_sparc
 #define helper_neon_qabs_s32 helper_neon_qabs_s32_sparc
 #define helper_neon_qabs_s64 helper_neon_qabs_s64_sparc

qemu/sparc64.h

@@ -1216,6 +1216,7 @@
 #define helper_gvec_orc helper_gvec_orc_sparc64
 #define helper_gvec_ors helper_gvec_ors_sparc64
 #define helper_gvec_pmul_b helper_gvec_pmul_b_sparc64
+#define helper_gvec_pmull_q helper_gvec_pmull_q_sparc64
 #define helper_gvec_qrdmlah_s16 helper_gvec_qrdmlah_s16_sparc64
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_sparc64
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_sparc64
@@ -1559,8 +1560,6 @@
 #define helper_neon_pmin_s8 helper_neon_pmin_s8_sparc64
 #define helper_neon_pmin_u16 helper_neon_pmin_u16_sparc64
 #define helper_neon_pmin_u8 helper_neon_pmin_u8_sparc64
-#define helper_neon_pmull_64_hi helper_neon_pmull_64_hi_sparc64
-#define helper_neon_pmull_64_lo helper_neon_pmull_64_lo_sparc64
 #define helper_neon_qabs_s16 helper_neon_qabs_s16_sparc64
 #define helper_neon_qabs_s32 helper_neon_qabs_s32_sparc64
 #define helper_neon_qabs_s64 helper_neon_qabs_s64_sparc64

qemu/target/arm/helper.h

@@ -559,9 +559,6 @@ DEF_HELPER_FLAGS_3(crc32_arm, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
 DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
 DEF_HELPER_2(dc_zva, void, env, i64)
 
-DEF_HELPER_FLAGS_2(neon_pmull_64_lo, TCG_CALL_NO_RWG_SE, i64, i64, i64)
-DEF_HELPER_FLAGS_2(neon_pmull_64_hi, TCG_CALL_NO_RWG_SE, i64, i64, i64)
-
 DEF_HELPER_FLAGS_5(gvec_qrdmlah_s16, TCG_CALL_NO_RWG,
                    void, ptr, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s16, TCG_CALL_NO_RWG,
@@ -693,6 +690,7 @@ DEF_HELPER_FLAGS_4(gvec_ushl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(gvec_ushl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 
 DEF_HELPER_FLAGS_4(gvec_pmul_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_pmull_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 
 #ifdef TARGET_ARM
 #define helper_clz helper_clz_arm

qemu/target/arm/neon_helper.c

@@ -2165,33 +2165,3 @@ void HELPER(neon_zip16)(void *vd, void *vm)
     rm[0] = m0;
     rd[0] = d0;
 }
-
-/* Helper function for 64 bit polynomial multiply case:
- * perform PolynomialMult(op1, op2) and return either the top or
- * bottom half of the 128 bit result.
- */
-uint64_t HELPER(neon_pmull_64_lo)(uint64_t op1, uint64_t op2)
-{
-    int bitnum;
-    uint64_t res = 0;
-
-    for (bitnum = 0; bitnum < 64; bitnum++) {
-        if (op1 & (1ULL << bitnum)) {
-            res ^= op2 << bitnum;
-        }
-    }
-    return res;
-}
-uint64_t HELPER(neon_pmull_64_hi)(uint64_t op1, uint64_t op2)
-{
-    int bitnum;
-    uint64_t res = 0;
-
-    /* bit 0 of op1 can't influence the high 64 bits at all */
-    for (bitnum = 1; bitnum < 64; bitnum++) {
-        if (op1 & (1ULL << bitnum)) {
-            res ^= op2 >> (64 - bitnum);
-        }
-    }
-    return res;
-}

qemu/target/arm/translate-a64.c

@@ -10947,31 +10947,6 @@ static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size,
     clear_vec_high(s, is_q, rd);
 }
 
-static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int rm)
-{
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
-    /* PMULL of 64 x 64 -> 128 is an odd special case because it
-     * is the only three-reg-diff instruction which produces a
-     * 128-bit wide result from a single operation. However since
-     * it's possible to calculate the two halves more or less
-     * separately we just use two helper calls.
-     */
-    TCGv_i64 tcg_op1 = tcg_temp_new_i64(tcg_ctx);
-    TCGv_i64 tcg_op2 = tcg_temp_new_i64(tcg_ctx);
-    TCGv_i64 tcg_res = tcg_temp_new_i64(tcg_ctx);
-
-    read_vec_element(s, tcg_op1, rn, is_q, MO_64);
-    read_vec_element(s, tcg_op2, rm, is_q, MO_64);
-    gen_helper_neon_pmull_64_lo(tcg_ctx, tcg_res, tcg_op1, tcg_op2);
-    write_vec_element(s, tcg_res, rd, 0, MO_64);
-    gen_helper_neon_pmull_64_hi(tcg_ctx, tcg_res, tcg_op1, tcg_op2);
-    write_vec_element(s, tcg_res, rd, 1, MO_64);
-
-    tcg_temp_free_i64(tcg_ctx, tcg_op1);
-    tcg_temp_free_i64(tcg_ctx, tcg_op2);
-    tcg_temp_free_i64(tcg_ctx, tcg_res);
-}
-
 /* AdvSIMD three different
  *   31  30  29 28       24 23  22  21 20  16 15    12 11 10 9    5 4    0
  * +---+---+---+-----------+------+---+------+--------+-----+------+------+
@@ -11036,7 +11011,9 @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
             if (!fp_access_check(s)) {
                 return;
             }
-            handle_pmull_64(s, is_q, rd, rn, rm);
+            /* The Q field specifies lo/hi half input for this insn.  */
+            gen_gvec_op3_ool(s, true, rd, rn, rm, is_q,
+                             gen_helper_gvec_pmull_q);
             return;
         }
         goto is_widening;

qemu/target/arm/translate.c

@@ -6003,23 +6003,11 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                  * outside the loop below as it only performs a single pass.
                  */
                 if (op == 14 && size == 2) {
-                    TCGv_i64 tcg_rn, tcg_rm, tcg_rd;
-
                     if (!dc_isar_feature(aa32_pmull, s)) {
                         return 1;
                     }
-                    tcg_rn = tcg_temp_new_i64(tcg_ctx);
+                    tcg_gen_gvec_3_ool(tcg_ctx, rd_ofs, rn_ofs, rm_ofs, 16, 16,
-                    tcg_rm = tcg_temp_new_i64(tcg_ctx);
+                                       0, gen_helper_gvec_pmull_q);
-                    tcg_rd = tcg_temp_new_i64(tcg_ctx);
-                    neon_load_reg64(s, tcg_rn, rn);
-                    neon_load_reg64(s, tcg_rm, rm);
-                    gen_helper_neon_pmull_64_lo(tcg_ctx, tcg_rd, tcg_rn, tcg_rm);
-                    neon_store_reg64(s, tcg_rd, rd);
-                    gen_helper_neon_pmull_64_hi(tcg_ctx, tcg_rd, tcg_rn, tcg_rm);
-                    neon_store_reg64(s, tcg_rd, rd + 1);
-                    tcg_temp_free_i64(tcg_ctx, tcg_rn);
-                    tcg_temp_free_i64(tcg_ctx, tcg_rm);
-                    tcg_temp_free_i64(tcg_ctx, tcg_rd);
                     return 0;
                 }
 

qemu/target/arm/vec_helper.c

@@ -1165,3 +1165,36 @@ void HELPER(gvec_pmul_b)(void *vd, void *vn, void *vm, uint32_t desc)
     }
     clear_tail(d, opr_sz, simd_maxsz(desc));
 }
+
+/*
+ * 64x64->128 polynomial multiply.
+ * Because of the lanes are not accessed in strict columns,
+ * this probably cannot be turned into a generic helper.
+ */
+void HELPER(gvec_pmull_q)(void *vd, void *vn, void *vm, uint32_t desc)
+{
+    intptr_t i, j, opr_sz = simd_oprsz(desc);
+    intptr_t hi = simd_data(desc);
+    uint64_t *d = vd, *n = vn, *m = vm;
+
+    for (i = 0; i < opr_sz / 8; i += 2) {
+        uint64_t nn = n[i + hi];
+        uint64_t mm = m[i + hi];
+        uint64_t rhi = 0;
+        uint64_t rlo = 0;
+
+        /* Bit 0 can only influence the low 64-bit result.  */
+        if (nn & 1) {
+            rlo = mm;
+        }
+
+        for (j = 1; j < 64; ++j) {
+            uint64_t mask = -((nn >> j) & 1);
+            rlo ^= (mm << j) & mask;
+            rhi ^= (mm >> (64 - j)) & mask;
+        }
+        d[i] = rlo;
+        d[i + 1] = rhi;
+    }
+    clear_tail(d, opr_sz, simd_maxsz(desc));
+}

qemu/x86_64.h

@@ -1216,6 +1216,7 @@
 #define helper_gvec_orc helper_gvec_orc_x86_64
 #define helper_gvec_ors helper_gvec_ors_x86_64
 #define helper_gvec_pmul_b helper_gvec_pmul_b_x86_64
+#define helper_gvec_pmull_q helper_gvec_pmull_q_x86_64
 #define helper_gvec_qrdmlah_s16 helper_gvec_qrdmlah_s16_x86_64
 #define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_x86_64
 #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_x86_64
@@ -1559,8 +1560,6 @@
 #define helper_neon_pmin_s8 helper_neon_pmin_s8_x86_64
 #define helper_neon_pmin_u16 helper_neon_pmin_u16_x86_64
 #define helper_neon_pmin_u8 helper_neon_pmin_u8_x86_64
-#define helper_neon_pmull_64_hi helper_neon_pmull_64_hi_x86_64
-#define helper_neon_pmull_64_lo helper_neon_pmull_64_lo_x86_64
 #define helper_neon_qabs_s16 helper_neon_qabs_s16_x86_64
 #define helper_neon_qabs_s32 helper_neon_qabs_s32_x86_64
 #define helper_neon_qabs_s64 helper_neon_qabs_s64_x86_64