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target-mips: add exception base to MIPS CPU

Browse source 
Replace hardcoded 0xbfc00000 with exception_base which is initialized with
this default address so there is no functional change here.
However, it is now exposed and consequently it will be possible to modify
it from outside of the CPU.

Backports commit 89777fd10fc3dd573c3b4d1b2efdd10af823c001 from qemu
This commit is contained in:
Leon Alrae 2018-02-25 03:18:07 -05:00 committed by Lioncash
parent 6f20d35cd1
commit c0b3938b88
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
8 changed files with 33 additions and 19 deletions
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7
qemu/header_gen.py
View file

@ -3203,8 +3203,10 @@ aarch64_symbols = (
mips_symbols = (
'cpu_mips_exec',
'cpu_mips_init',
'cpu_mips_get_random',
'cpu_mips_get_count',
'cpu_set_exception_base',
'cpu_mips_store_cause',
'cpu_mips_store_count',
'cpu_mips_store_compare',
@ -3212,12 +3214,9 @@ mips_symbols = (
'cpu_mips_start_count',
'cpu_mips_stop_count',
'cpu_mips_tlb_flush',
'mips_machine_init',
'cpu_mips_kseg0_to_phys',
'cpu_mips_phys_to_kseg0',
'cpu_mips_kvm_um_phys_to_kseg0',
'mips_cpu_register_types',
'cpu_mips_init',
'cpu_state_reset',
'do_raise_exception_err',
'float_class_d',
@ -4143,6 +4142,8 @@ mips_symbols = (
'helper_dmfc0_watchlo',
'helper_dmtc0_entrylo0',
'helper_dmtc0_entrylo1',
'mips_cpu_register_types',
'mips_machine_init',
'mips_reg_reset',
'mips_reg_read',
'mips_reg_write',

7
qemu/mips.h
View file

@ -3148,8 +3148,10 @@
#define xscale_cpar_write xscale_cpar_write_mips
#define xscale_cp_reginfo xscale_cp_reginfo_mips
#define cpu_mips_exec cpu_mips_exec_mips
#define cpu_mips_init cpu_mips_init_mips
#define cpu_mips_get_random cpu_mips_get_random_mips
#define cpu_mips_get_count cpu_mips_get_count_mips
#define cpu_set_exception_base cpu_set_exception_base_mips
#define cpu_mips_store_cause cpu_mips_store_cause_mips
#define cpu_mips_store_count cpu_mips_store_count_mips
#define cpu_mips_store_compare cpu_mips_store_compare_mips
@ -3157,12 +3159,9 @@
#define cpu_mips_start_count cpu_mips_start_count_mips
#define cpu_mips_stop_count cpu_mips_stop_count_mips
#define cpu_mips_tlb_flush cpu_mips_tlb_flush_mips
#define mips_machine_init mips_machine_init_mips
#define cpu_mips_kseg0_to_phys cpu_mips_kseg0_to_phys_mips
#define cpu_mips_phys_to_kseg0 cpu_mips_phys_to_kseg0_mips
#define cpu_mips_kvm_um_phys_to_kseg0 cpu_mips_kvm_um_phys_to_kseg0_mips
#define mips_cpu_register_types mips_cpu_register_types_mips
#define cpu_mips_init cpu_mips_init_mips
#define cpu_state_reset cpu_state_reset_mips
#define do_raise_exception_err do_raise_exception_err_mips
#define float_class_d float_class_d_mips
@ -4088,6 +4087,8 @@
#define helper_dmfc0_watchlo helper_dmfc0_watchlo_mips
#define helper_dmtc0_entrylo0 helper_dmtc0_entrylo0_mips
#define helper_dmtc0_entrylo1 helper_dmtc0_entrylo1_mips
#define mips_cpu_register_types mips_cpu_register_types_mips
#define mips_machine_init mips_machine_init_mips
#define mips_reg_reset mips_reg_reset_mips
#define mips_reg_read mips_reg_read_mips
#define mips_reg_write mips_reg_write_mips

7
qemu/mips64.h
View file

@ -3148,8 +3148,10 @@
#define xscale_cpar_write xscale_cpar_write_mips64
#define xscale_cp_reginfo xscale_cp_reginfo_mips64
#define cpu_mips_exec cpu_mips_exec_mips64
#define cpu_mips_init cpu_mips_init_mips64
#define cpu_mips_get_random cpu_mips_get_random_mips64
#define cpu_mips_get_count cpu_mips_get_count_mips64
#define cpu_set_exception_base cpu_set_exception_base_mips64
#define cpu_mips_store_cause cpu_mips_store_cause_mips64
#define cpu_mips_store_count cpu_mips_store_count_mips64
#define cpu_mips_store_compare cpu_mips_store_compare_mips64
@ -3157,12 +3159,9 @@
#define cpu_mips_start_count cpu_mips_start_count_mips64
#define cpu_mips_stop_count cpu_mips_stop_count_mips64
#define cpu_mips_tlb_flush cpu_mips_tlb_flush_mips64
#define mips_machine_init mips_machine_init_mips64
#define cpu_mips_kseg0_to_phys cpu_mips_kseg0_to_phys_mips64
#define cpu_mips_phys_to_kseg0 cpu_mips_phys_to_kseg0_mips64
#define cpu_mips_kvm_um_phys_to_kseg0 cpu_mips_kvm_um_phys_to_kseg0_mips64
#define mips_cpu_register_types mips_cpu_register_types_mips64
#define cpu_mips_init cpu_mips_init_mips64
#define cpu_state_reset cpu_state_reset_mips64
#define do_raise_exception_err do_raise_exception_err_mips64
#define float_class_d float_class_d_mips64
@ -4088,6 +4087,8 @@
#define helper_dmfc0_watchlo helper_dmfc0_watchlo_mips64
#define helper_dmtc0_entrylo0 helper_dmtc0_entrylo0_mips64
#define helper_dmtc0_entrylo1 helper_dmtc0_entrylo1_mips64
#define mips_cpu_register_types mips_cpu_register_types_mips64
#define mips_machine_init mips_machine_init_mips64
#define mips_reg_reset mips_reg_reset_mips64
#define mips_reg_read mips_reg_read_mips64
#define mips_reg_write mips_reg_write_mips64

7
qemu/mips64el.h
View file

@ -3148,8 +3148,10 @@
#define xscale_cpar_write xscale_cpar_write_mips64el
#define xscale_cp_reginfo xscale_cp_reginfo_mips64el
#define cpu_mips_exec cpu_mips_exec_mips64el
#define cpu_mips_init cpu_mips_init_mips64el
#define cpu_mips_get_random cpu_mips_get_random_mips64el
#define cpu_mips_get_count cpu_mips_get_count_mips64el
#define cpu_set_exception_base cpu_set_exception_base_mips64el
#define cpu_mips_store_cause cpu_mips_store_cause_mips64el
#define cpu_mips_store_count cpu_mips_store_count_mips64el
#define cpu_mips_store_compare cpu_mips_store_compare_mips64el
@ -3157,12 +3159,9 @@
#define cpu_mips_start_count cpu_mips_start_count_mips64el
#define cpu_mips_stop_count cpu_mips_stop_count_mips64el
#define cpu_mips_tlb_flush cpu_mips_tlb_flush_mips64el
#define mips_machine_init mips_machine_init_mips64el
#define cpu_mips_kseg0_to_phys cpu_mips_kseg0_to_phys_mips64el
#define cpu_mips_phys_to_kseg0 cpu_mips_phys_to_kseg0_mips64el
#define cpu_mips_kvm_um_phys_to_kseg0 cpu_mips_kvm_um_phys_to_kseg0_mips64el
#define mips_cpu_register_types mips_cpu_register_types_mips64el
#define cpu_mips_init cpu_mips_init_mips64el
#define cpu_state_reset cpu_state_reset_mips64el
#define do_raise_exception_err do_raise_exception_err_mips64el
#define float_class_d float_class_d_mips64el
@ -4088,6 +4087,8 @@
#define helper_dmfc0_watchlo helper_dmfc0_watchlo_mips64el
#define helper_dmtc0_entrylo0 helper_dmtc0_entrylo0_mips64el
#define helper_dmtc0_entrylo1 helper_dmtc0_entrylo1_mips64el
#define mips_cpu_register_types mips_cpu_register_types_mips64el
#define mips_machine_init mips_machine_init_mips64el
#define mips_reg_reset mips_reg_reset_mips64el
#define mips_reg_read mips_reg_read_mips64el
#define mips_reg_write mips_reg_write_mips64el

7
qemu/mipsel.h
View file

@ -3148,8 +3148,10 @@
#define xscale_cpar_write xscale_cpar_write_mipsel
#define xscale_cp_reginfo xscale_cp_reginfo_mipsel
#define cpu_mips_exec cpu_mips_exec_mipsel
#define cpu_mips_init cpu_mips_init_mipsel
#define cpu_mips_get_random cpu_mips_get_random_mipsel
#define cpu_mips_get_count cpu_mips_get_count_mipsel
#define cpu_set_exception_base cpu_set_exception_base_mipsel
#define cpu_mips_store_cause cpu_mips_store_cause_mipsel
#define cpu_mips_store_count cpu_mips_store_count_mipsel
#define cpu_mips_store_compare cpu_mips_store_compare_mipsel
@ -3157,12 +3159,9 @@
#define cpu_mips_start_count cpu_mips_start_count_mipsel
#define cpu_mips_stop_count cpu_mips_stop_count_mipsel
#define cpu_mips_tlb_flush cpu_mips_tlb_flush_mipsel
#define mips_machine_init mips_machine_init_mipsel
#define cpu_mips_kseg0_to_phys cpu_mips_kseg0_to_phys_mipsel
#define cpu_mips_phys_to_kseg0 cpu_mips_phys_to_kseg0_mipsel
#define cpu_mips_kvm_um_phys_to_kseg0 cpu_mips_kvm_um_phys_to_kseg0_mipsel
#define mips_cpu_register_types mips_cpu_register_types_mipsel
#define cpu_mips_init cpu_mips_init_mipsel
#define cpu_state_reset cpu_state_reset_mipsel
#define do_raise_exception_err do_raise_exception_err_mipsel
#define float_class_d float_class_d_mipsel
@ -4088,6 +4087,8 @@
#define helper_dmfc0_watchlo helper_dmfc0_watchlo_mipsel
#define helper_dmtc0_entrylo0 helper_dmtc0_entrylo0_mipsel
#define helper_dmtc0_entrylo1 helper_dmtc0_entrylo1_mipsel
#define mips_cpu_register_types mips_cpu_register_types_mipsel
#define mips_machine_init mips_machine_init_mipsel
#define mips_reg_reset mips_reg_reset_mipsel
#define mips_reg_read mips_reg_read_mipsel
#define mips_reg_write mips_reg_write_mipsel

2
qemu/target-mips/cpu.h
View file

@ -611,6 +611,7 @@ struct CPUMIPSState {
const mips_def_t *cpu_model;
//void *irq[8];
//QEMUTimer *timer; /* Internal timer */
target_ulong exception_base; /* ExceptionBase input to the core */
// Unicorn engine
struct uc_struct *uc;
@ -799,6 +800,7 @@ int cpu_mips_exec(struct uc_struct *uc, CPUState *cpu);
void mips_tcg_init(struct uc_struct *uc);
MIPSCPU *cpu_mips_init(struct uc_struct *uc, const char *cpu_model);
int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
void cpu_set_exception_base(struct uc_struct *uc, int vp_index, target_ulong address);
/* TODO QOM'ify CPU reset and remove */
void cpu_state_reset(CPUMIPSState *s);

6
qemu/target-mips/helper.c
View file

@ -629,7 +629,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
/* EJTAG probe trap enable is not implemented... */
if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1U << CP0Ca_BD);
env->active_tc.PC = (int32_t)0xBFC00480;
env->active_tc.PC = env->exception_base + 0x480;
set_hflags_for_handler(env);
break;
case EXCP_RESET:
@ -656,7 +656,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->hflags &= ~(MIPS_HFLAG_KSU);
if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1U << CP0Ca_BD);
env->active_tc.PC = (int32_t)0xBFC00000;
env->active_tc.PC = env->exception_base;
set_hflags_for_handler(env);
break;
case EXCP_EXT_INTERRUPT:
@ -838,7 +838,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
}
env->hflags &= ~MIPS_HFLAG_BMASK;
if (env->CP0_Status & (1 << CP0St_BEV)) {
env->active_tc.PC = (int32_t)0xBFC00200;
env->active_tc.PC = env->exception_base + 0x200;
} else {
env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
}

9
qemu/target-mips/translate.c
View file

@ -20315,6 +20315,7 @@ MIPSCPU *cpu_mips_init(struct uc_struct *uc, const char *cpu_model)
cpu = MIPS_CPU(uc, object_new(uc, TYPE_MIPS_CPU));
env = &cpu->env;
env->cpu_model = def;
env->exception_base = (int32_t)0xBFC00000;
#ifndef CONFIG_USER_ONLY
mmu_init(env, def);
@ -20327,6 +20328,12 @@ MIPSCPU *cpu_mips_init(struct uc_struct *uc, const char *cpu_model)
return cpu;
}
void cpu_set_exception_base(struct uc_struct *uc, int vp_index, target_ulong address)
{
MIPSCPU *vp = MIPS_CPU(uc, qemu_get_cpu(uc, vp_index));
vp->env.exception_base = address;
}
void cpu_state_reset(CPUMIPSState *env)
{
MIPSCPU *cpu = mips_env_get_cpu(env);
@ -20417,7 +20424,7 @@ void cpu_state_reset(CPUMIPSState *env)
} else {
env->CP0_ErrorEPC = env->active_tc.PC;
}
env->active_tc.PC = (int32_t)0xBFC00000;
env->active_tc.PC = env->exception_base;
env->CP0_Random = env->tlb->nb_tlb - 1;
env->tlb->tlb_in_use = env->tlb->nb_tlb;
env->CP0_Wired = 0;