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target-arm: Add QOM property for Secure memory region

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Add QOM property to the ARM CPU which boards can use to tell us what
memory region to use for secure accesses. Nonsecure accesses
go via the memory region specified with the base CPU class 'memory'
property.

By default, if no secure region is specified it is the same as the
nonsecure region, and if no nonsecure region is specified we will use
address_space_memory.

Backports commit 9e273ef2174d7cd5b14a16d8638812541d3eb6bb from qemu
This commit is contained in:
Peter Maydell 2018-02-18 22:08:20 -05:00 committed by Lioncash
parent fd4e62bc1d
commit c13497c369
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 52 additions and 0 deletions
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3
qemu/target-arm/cpu-qom.h
View file

@ -86,6 +86,9 @@ typedef struct ARMCPU {
/* GPIO outputs for generic timer */ /* GPIO outputs for generic timer */
//qemu_irq gt_timer_outputs[NUM_GTIMERS]; //qemu_irq gt_timer_outputs[NUM_GTIMERS];
/* MemoryRegion to use for secure physical accesses */
MemoryRegion *secure_memory;
/* 'compatible' string for this CPU for Linux device trees */ /* 'compatible' string for this CPU for Linux device trees */
const char *dtb_compatible; const char *dtb_compatible;

43
qemu/target-arm/cpu.c
View file

@ -420,6 +420,24 @@ static void arm_cpu_post_init(struct uc_struct *uc, Object *obj)
//qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, //qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
// &error_abort); // &error_abort);
} }
if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
/* Add the has_el3 state CPU property only if EL3 is allowed. This will
* prevent "has_el3" from existing on CPUs which cannot support EL3.
*/
//qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
// &error_abort);
#ifndef CONFIG_USER_ONLY
/* Unicorn: commented out
object_property_add_link(obj, "secure-memory",
TYPE_MEMORY_REGION,
(Object **)&cpu->secure_memory,
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_UNREF_ON_RELEASE,
&error_abort);*/
#endif
}
} }
static void arm_cpu_finalizefn(struct uc_struct *uc, Object *obj, void *opaque) static void arm_cpu_finalizefn(struct uc_struct *uc, Object *obj, void *opaque)
@ -539,6 +557,31 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
register_cp_regs_for_features(cpu); register_cp_regs_for_features(cpu);
arm_cpu_register_gdb_regs_for_features(cpu); arm_cpu_register_gdb_regs_for_features(cpu);
#ifndef CONFIG_USER_ONLY
if (cpu->has_el3) {
cs->num_ases = 2;
} else {
cs->num_ases = 1;
}
if (cpu->has_el3) {
AddressSpace *as;
if (!cpu->secure_memory) {
cpu->secure_memory = cs->memory;
}
as = address_space_init_shareable(uc,
cpu->secure_memory,
"cpu-secure-memory");
cpu_address_space_init(cs, as, ARMASIdx_S);
}
cpu_address_space_init(cs,
address_space_init_shareable(uc,
cs->memory,
"cpu-memory"),
ARMASIdx_NS);
#endif
init_cpreg_list(cpu); init_cpreg_list(cpu);
qemu_init_vcpu(cs); qemu_init_vcpu(cs);

6
qemu/target-arm/cpu.h
View file

@ -1723,6 +1723,12 @@ typedef enum ARMMMUIdx {
#define MMU_USER_IDX 0 #define MMU_USER_IDX 0
/* Indexes used when registering address spaces with cpu_address_space_init */
typedef enum ARMASIdx {
ARMASIdx_NS = 0,
ARMASIdx_S = 1,
} ARMASIdx;
/* Return the exception level we're running at if this is our mmu_idx */ /* Return the exception level we're running at if this is our mmu_idx */
static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
{ {