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target-sparc: use explicit mmu register pointers

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Use explicit register pointers while accessing D/I-MMU registers.
Call cpu_unassigned_access on access to missing registers.

Backports commit 20395e63375358bf6dd147057aaf998abf7abdb9 from qemu
This commit is contained in:
Artyom Tarasenko 2018-03-01 20:36:20 -05:00 committed by Lioncash
parent be8357f8b5
commit c1c88e147d
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 58 additions and 10 deletions
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4
qemu/target-sparc/cpu.h
View file

@ -440,6 +440,8 @@ struct CPUSPARCState {
uint64_t sfar;
uint64_t tsb;
uint64_t tag_access;
uint64_t virtual_watchpoint;
uint64_t physical_watchpoint;
} immu;
};
union {
@ -452,6 +454,8 @@ struct CPUSPARCState {
uint64_t sfar;
uint64_t tsb;
uint64_t tag_access;
uint64_t virtual_watchpoint;
uint64_t physical_watchpoint;
} dmmu;
};
SparcTLBEntry itlb[64];

64
qemu/target-sparc/ldst_helper.c
View file

@ -1231,13 +1231,25 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
{
int reg = (addr >> 3) & 0xf;
if (reg == 0) {
/* I-TSB Tag Target register */
switch (reg) {
case 0:
/* 0x00 I-TSB Tag Target register */
ret = ultrasparc_tag_target(env->immu.tag_access);
} else {
ret = env->immuregs[reg];
break;
case 3: /* SFSR */
ret = env->immu.sfsr;
break;
case 5: /* TSB access */
ret = env->immu.tsb;
break;
case 6:
/* 0x30 I-TSB Tag Access register */
ret = env->immu.tag_access;
break;
default:
cpu_unassigned_access(cs, addr, false, false, 1, size);
ret = 0;
}
break;
}
case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer */
@ -1274,11 +1286,38 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
{
int reg = (addr >> 3) & 0xf;
if (reg == 0) {
/* D-TSB Tag Target register */
switch (reg) {
case 0:
/* 0x00 D-TSB Tag Target register */
ret = ultrasparc_tag_target(env->dmmu.tag_access);
} else {
ret = env->dmmuregs[reg];
break;
case 1: /* 0x08 Primary Context */
ret = env->dmmu.mmu_primary_context;
break;
case 2: /* 0x10 Secondary Context */
ret = env->dmmu.mmu_secondary_context;
break;
case 3: /* SFSR */
ret = env->dmmu.sfsr;
break;
case 4: /* 0x20 SFAR */
ret = env->dmmu.sfar;
break;
case 5: /* 0x28 TSB access */
ret = env->dmmu.tsb;
break;
case 6: /* 0x30 D-TSB Tag Access register */
ret = env->dmmu.tag_access;
break;
case 7:
ret = env->dmmu.virtual_watchpoint;
break;
case 8:
ret = env->dmmu.physical_watchpoint;
break;
default:
cpu_unassigned_access(cs, addr, false, false, 1, size);
ret = 0;
}
break;
}
@ -1467,6 +1506,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
case 8:
return;
default:
cpu_unassigned_access(cs, addr, true, false, 1, size);
break;
}
@ -1537,9 +1577,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
env->dmmu.tag_access = val;
break;
case 7: /* Virtual Watchpoint */
env->dmmu.virtual_watchpoint = val;
break;
case 8: /* Physical Watchpoint */
env->dmmu.physical_watchpoint = val;
break;
default:
env->dmmuregs[reg] = val;
cpu_unassigned_access(cs, addr, true, false, 1, size);
break;
}