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tcg: check CF_PARALLEL instead of parallel_cpus

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Thereby decoupling the resulting translated code from the current state
of the system.

The tb->cflags field is not passed to tcg generation functions. So
we add a field to TCGContext, storing there a copy of tb->cflags.

Most architectures have <= 32 registers, which results in a 4-byte hole
in TCGContext. Use this hole for the new field.

Backports commit e82d5a2460b0e176128027651ff9b104e4bdf5cc from qemu
This commit is contained in:
Emilio G. Cota 2019-05-06 00:46:32 -04:00 committed by Lioncash
parent 175a5223ad
commit c1e26c4e35
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 7 additions and 5 deletions
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1
qemu/accel/tcg/translate-all.c
View file

@ -1360,6 +1360,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tb->cs_base = cs_base; tb->cs_base = cs_base;
tb->flags = flags; tb->flags = flags;
tb->cflags = cflags; tb->cflags = cflags;
tcg_ctx->tb_cflags = cflags;
tb_overflow: tb_overflow:
#ifdef CONFIG_PROFILER #ifdef CONFIG_PROFILER

10
qemu/tcg/tcg-op.c
View file

@ -97,7 +97,7 @@ void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2,
void tcg_gen_mb(TCGContext *ctx, TCGBar mb_type) void tcg_gen_mb(TCGContext *ctx, TCGBar mb_type)
{ {
if (ctx->uc->parallel_cpus) { if (ctx->tb_cflags & CF_PARALLEL) {
tcg_gen_op1(ctx, INDEX_op_mb, mb_type); tcg_gen_op1(ctx, INDEX_op_mb, mb_type);
} }
} }
@ -3064,7 +3064,7 @@ void tcg_gen_atomic_cmpxchg_i32(TCGContext *s,
{ {
memop = tcg_canonicalize_memop(memop, 0, 0); memop = tcg_canonicalize_memop(memop, 0, 0);
if (!s->uc->parallel_cpus) { if (!(s->tb_cflags & CF_PARALLEL)) {
TCGv_i32 t1 = tcg_temp_new_i32(s); TCGv_i32 t1 = tcg_temp_new_i32(s);
TCGv_i32 t2 = tcg_temp_new_i32(s); TCGv_i32 t2 = tcg_temp_new_i32(s);
@ -3109,7 +3109,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGContext *s,
{ {
memop = tcg_canonicalize_memop(memop, 1, 0); memop = tcg_canonicalize_memop(memop, 1, 0);
if (!s->uc->parallel_cpus) { if (!(s->tb_cflags & CF_PARALLEL)) {
TCGv_i64 t1 = tcg_temp_new_i64(s); TCGv_i64 t1 = tcg_temp_new_i64(s);
TCGv_i64 t2 = tcg_temp_new_i64(s); TCGv_i64 t2 = tcg_temp_new_i64(s);
@ -3290,7 +3290,7 @@ static void * const table_##NAME[16] = { \
void tcg_gen_atomic_##NAME##_i32 \ void tcg_gen_atomic_##NAME##_i32 \
(TCGContext *s, TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \ (TCGContext *s, TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \
{ \ { \
if (s->uc->parallel_cpus) { \ if (s->tb_cflags & CF_PARALLEL) { \
do_atomic_op_i32(s, ret, addr, val, idx, memop, table_##NAME); \ do_atomic_op_i32(s, ret, addr, val, idx, memop, table_##NAME); \
} else { \ } else { \
do_nonatomic_op_i32(s, ret, addr, val, idx, memop, NEW, \ do_nonatomic_op_i32(s, ret, addr, val, idx, memop, NEW, \
@ -3300,7 +3300,7 @@ void tcg_gen_atomic_##NAME##_i32 \
void tcg_gen_atomic_##NAME##_i64 \ void tcg_gen_atomic_##NAME##_i64 \
(TCGContext *s, TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, TCGMemOp memop) \ (TCGContext *s, TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, TCGMemOp memop) \
{ \ { \
if (s->uc->parallel_cpus) { \ if (s->tb_cflags & CF_PARALLEL) { \
do_atomic_op_i64(s, ret, addr, val, idx, memop, table_##NAME); \ do_atomic_op_i64(s, ret, addr, val, idx, memop, table_##NAME); \
} else { \ } else { \
do_nonatomic_op_i64(s, ret, addr, val, idx, memop, NEW, \ do_nonatomic_op_i64(s, ret, addr, val, idx, memop, NEW, \

1
qemu/tcg/tcg.h
View file

@ -770,6 +770,7 @@ struct TCGContext {
uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */ uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */
TCGRegSet reserved_regs; TCGRegSet reserved_regs;
uint32_t tb_cflags; /* cflags of the current TB */
intptr_t current_frame_offset; intptr_t current_frame_offset;
intptr_t frame_start; intptr_t frame_start;
intptr_t frame_end; intptr_t frame_end;