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target-mips: microMIPS32 R6 POOL32{I, C} instructions

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Add new microMIPS32 Release 6 POOL32I/POOL32C type instructions

Backports commit 3b4a5489447e7ed17cc504572cf729833853e7ab from qemu
This commit is contained in:
Yongbok Kim 2018-02-13 22:18:00 -05:00 committed by Lioncash
parent fe7e49dc20
commit c2550bc28a
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 21 additions and 6 deletions
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23
qemu/target-mips/translate.c
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@ -14757,9 +14757,18 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_TGEIU; mips32_op = OPC_TGEIU;
goto do_trapi; goto do_trapi;
case TNEI: case TNEI: /* SYNCI */
if (ctx->insn_flags & ISA_MIPS32R6) {
/* SYNCI */
/* Break the TB to be able to sync copied instructions
immediately */
ctx->bstate = BS_STOP;
} else {
/* TNEI */
mips32_op = OPC_TNEI; mips32_op = OPC_TNEI;
goto do_trapi; goto do_trapi;
}
break;
case TEQI: case TEQI:
check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn_opc_removed(ctx, ISA_MIPS32R6);
mips32_op = OPC_TEQI; mips32_op = OPC_TEQI;
@ -14832,6 +14841,8 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
break; break;
case POOL32C: case POOL32C:
minor = (ctx->opcode >> 12) & 0xf; minor = (ctx->opcode >> 12) & 0xf;
offset = sextract32(ctx->opcode, 0,
(ctx->insn_flags & ISA_MIPS32R6) ? 9 : 12);
switch (minor) { switch (minor) {
case LWL: case LWL:
check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn_opc_removed(ctx, ISA_MIPS32R6);
@ -14889,23 +14900,27 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
mips32_op = OPC_LL; mips32_op = OPC_LL;
goto do_ld_lr; goto do_ld_lr;
do_ld_lr: do_ld_lr:
gen_ld(ctx, mips32_op, rt, rs, SIMM(ctx->opcode, 0, 12)); gen_ld(ctx, mips32_op, rt, rs, offset);
break; break;
do_st_lr: do_st_lr:
gen_st(ctx, mips32_op, rt, rs, SIMM(ctx->opcode, 0, 12)); gen_st(ctx, mips32_op, rt, rs, SIMM(ctx->opcode, 0, 12));
break; break;
case SC: case SC:
gen_st_cond(ctx, OPC_SC, rt, rs, SIMM(ctx->opcode, 0, 12)); gen_st_cond(ctx, OPC_SC, rt, rs, offset);
break; break;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case SCD: case SCD:
check_insn(ctx, ISA_MIPS3); check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx); check_mips_64(ctx);
gen_st_cond(ctx, OPC_SCD, rt, rs, SIMM(ctx->opcode, 0, 12)); gen_st_cond(ctx, OPC_SCD, rt, rs, offset);
break; break;
#endif #endif
case PREF: case PREF:
/* Treat as no-op */ /* Treat as no-op */
if ((ctx->insn_flags & ISA_MIPS32R6) && (rt >= 24)) {
/* hint codes 24-31 are reserved and signal RI */
generate_exception(ctx, EXCP_RI);
}
break; break;
default: default:
MIPS_INVAL("pool32c"); MIPS_INVAL("pool32c");