target-arm: Add the pmceid0 and pmceid1 registers

Backports commit 4054bfa9e7986c9b7d2bf70f9e10af9647e376fc from qemu
This commit is contained in:
Alistair Francis 2018-02-20 15:22:29 -05:00 committed by Lioncash
parent 57a9474cc7
commit c31856e34e
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
4 changed files with 18 additions and 0 deletions

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@ -147,6 +147,8 @@ typedef struct ARMCPU {
uint32_t id_pfr0;
uint32_t id_pfr1;
uint32_t id_dfr0;
uint32_t pmceid0;
uint32_t pmceid1;
uint32_t id_afr0;
uint32_t id_mmfr0;
uint32_t id_mmfr1;

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@ -1043,6 +1043,8 @@ static void cortex_a15_initfn(struct uc_struct *uc, Object *obj, void *opaque)
cpu->id_pfr0 = 0x00001131;
cpu->id_pfr1 = 0x00011011;
cpu->id_dfr0 = 0x02010555;
cpu->pmceid0 = 0x00000000;
cpu->pmceid1 = 0x00000000;
cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x10201105;
cpu->id_mmfr1 = 0x20000000;

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@ -118,6 +118,8 @@ static void aarch64_a57_initfn(struct uc_struct *uc, Object *obj, void *opaque)
cpu->id_isar5 = 0x00011121;
cpu->id_aa64pfr0 = 0x00002222;
cpu->id_aa64dfr0 = 0x10305106;
cpu->pmceid0 = 0x00000000;
cpu->pmceid1 = 0x00000000;
cpu->id_aa64isar0 = 0x00011120;
cpu->id_aa64mmfr0 = 0x00001124;
cpu->dbgdidr = 0x3516d000;

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@ -3789,6 +3789,18 @@ void register_cp_regs_for_features(ARMCPU *cpu)
ARM_CP_CONST, PL1_R, 0, NULL, cpu->mvfr1 },
{ "MVFR2_EL1", 0,0,3, 3,0,2, ARM_CP_STATE_AA64,
ARM_CP_CONST, PL1_R, 0, NULL, cpu->mvfr2 },
{ "PMCEID0", 15,9,12, 0,0,6, ARM_CP_STATE_AA32, ARM_CP_CONST,
PL0_R, 0, NULL, cpu->pmceid0, 0, {0, 0},
pmreg_access },
{ "PMCEID0_EL0", 0,9,12, 3,3,6, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL0_R, 0, NULL, cpu->pmceid0, 0, {0, 0},
pmreg_access },
{ "PMCEID1", 15,9,12, 0,0,7, ARM_CP_STATE_AA32, ARM_CP_CONST,
PL0_R, 0, NULL, cpu->pmceid1, 0, {0, 0},
pmreg_access },
{ "PMCEID1_EL0", 0,9,12, 3,3,7, ARM_CP_STATE_AA64, ARM_CP_CONST,
PL0_R, 0, NULL, cpu->pmceid1, 0, {0, 0},
pmreg_access },
REGINFO_SENTINEL
};
/* RVBAR_EL1 is only implemented if EL1 is the highest EL */