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target/riscv: Return the exception from invalid CSR accesses

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When performing a CSR access let's return a negative exception value on
an error instead of -1. This will allow us to specify the exception in
future patches.

Backports 57cb2083e638bb28616c059cbf067d99552a04bb
This commit is contained in:
Alistair Francis 2021-03-08 13:49:06 -05:00 committed by Lioncash
parent dd9f854edb
commit c3d9e15f02
2 changed files with 41 additions and 35 deletions
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58
qemu/target/riscv/csr.c
View file

@ -49,8 +49,8 @@ static int fs(CPURISCVState *env, int csrno)
if ((csrno == CSR_FCSR) && (env->misa & RVV)) {
return 0;
}
if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
return 0;
@ -93,7 +93,7 @@ static int hmode(CPURISCVState *env, int csrno)
}
}
return -1;
return -RISCV_EXCP_ILLEGAL_INST;
}
static int pmp(CPURISCVState *env, int csrno)
@ -106,8 +106,8 @@ static int pmp(CPURISCVState *env, int csrno)
static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;;
}
#endif
*val = riscv_cpu_get_fflags(env);
@ -117,8 +117,8 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;;
}
env->mstatus |= MSTATUS_FS;
#endif
@ -129,8 +129,8 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;;
}
#endif
*val = env->frm;
@ -140,8 +140,8 @@ static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;;
}
env->mstatus |= MSTATUS_FS;
#endif
@ -152,8 +152,8 @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;;
}
#endif
*val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
@ -168,8 +168,8 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !(env->mstatus & MSTATUS_FS)) {
return -1;
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return -RISCV_EXCP_ILLEGAL_INST;;
}
env->mstatus |= MSTATUS_FS;
#endif
@ -291,7 +291,7 @@ static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
if (!env->rdtime_fn) {
return -1;
return -RISCV_EXCP_ILLEGAL_INST;
}
*val = env->rdtime_fn() + delta;
@ -304,7 +304,7 @@ static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
if (!env->rdtime_fn) {
return -1;
return -RISCV_EXCP_ILLEGAL_INST;
}
*val = (env->rdtime_fn() + delta) >> 32;
@ -570,7 +570,7 @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
{
if (env->priv_ver < PRIV_VERSION_1_11_0) {
return -1;
return -RISCV_EXCP_ILLEGAL_INST;
}
*val = env->mcounteren;
return 0;
@ -580,7 +580,7 @@ static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
{
if (env->priv_ver < PRIV_VERSION_1_11_0) {
return -1;
return -RISCV_EXCP_ILLEGAL_INST;
}
env->mcounteren = val;
return 0;
@ -807,7 +807,7 @@ static int read_satp(CPURISCVState *env, int csrno, target_ulong *val)
}
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
return -1;
return -RISCV_EXCP_ILLEGAL_INST;
} else {
*val = env->satp;
}
@ -824,7 +824,7 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
{
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
return -1;
return -RISCV_EXCP_ILLEGAL_INST;
} else {
if((val ^ env->satp) & SATP_ASID) {
tlb_flush(env_cpu(env));
@ -994,7 +994,7 @@ static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val)
static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
{
if (!env->rdtime_fn) {
return -1;
return -RISCV_EXCP_ILLEGAL_INST;
}
#if defined(TARGET_RISCV32)
@ -1008,7 +1008,7 @@ static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
{
if (!env->rdtime_fn) {
return -1;
return -RISCV_EXCP_ILLEGAL_INST;
}
#if defined(TARGET_RISCV32)
@ -1023,7 +1023,7 @@ static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
{
if (!env->rdtime_fn) {
return -1;
return -RISCV_EXCP_ILLEGAL_INST;
}
*val = env->htimedelta >> 32;
@ -1033,7 +1033,7 @@ static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val)
{
if (!env->rdtime_fn) {
return -1;
return -RISCV_EXCP_ILLEGAL_INST;
}
env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
@ -1229,18 +1229,18 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
}
if ((write_mask && read_only) ||
(!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
return -1;
return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
/* ensure the CSR extension is enabled. */
if (!cpu->cfg.ext_icsr) {
return -1;
return -RISCV_EXCP_ILLEGAL_INST;
}
/* check predicate */
if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) {
return -1;
return -RISCV_EXCP_ILLEGAL_INST;
}
/* execute combined read/write operation if it exists */
@ -1250,7 +1250,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
/* if no accessor exists then return failure */
if (!csr_ops[csrno].read) {
return -1;
return -RISCV_EXCP_ILLEGAL_INST;
}
/* read old value */

18
qemu/target/riscv/op_helper.c
View file

@ -43,8 +43,10 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
target_ulong csr)
{
target_ulong val = 0;
if (riscv_csrrw(env, csr, &val, src, -1) < 0) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
int ret = riscv_csrrw(env, csr, &val, src, -1);
if (ret < 0) {
riscv_raise_exception(env, -ret, GETPC());
}
return val;
}
@ -53,8 +55,10 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
target_ulong csr, target_ulong rs1_pass)
{
target_ulong val = 0;
if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
int ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0);
if (ret < 0) {
riscv_raise_exception(env, -ret, GETPC());
}
return val;
}
@ -63,8 +67,10 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
target_ulong csr, target_ulong rs1_pass)
{
target_ulong val = 0;
if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
int ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0);
if (ret < 0) {
riscv_raise_exception(env, -ret, GETPC());
}
return val;
}