yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-01-08 22:15:28 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/arm/translate: Synchronize with Qemu

Browse source
This commit is contained in:
Lioncash 2019-04-26 19:31:04 -04:00
parent 9dfe2b527b
commit c3df12e534
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
5 changed files with 87 additions and 74 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

22
qemu/glib_compat.c
View file

@ -1535,6 +1535,28 @@ static void g_hash_table_insert_internal (GHashTable *hash_table,
}
}
GList *
g_hash_table_get_keys (GHashTable *hash_table)
{
gint i;
GList *retval;
if (hash_table == NULL) {
return NULL;
}
retval = NULL;
for (i = 0; i < hash_table->size; i++)
{
GHashNode *node = &hash_table->nodes [i];
if (node->key_hash > 1)
retval = g_list_prepend (retval, node->key);
}
return retval;
}
/**
* g_hash_table_insert:
* @hash_table: a #GHashTable.

1
qemu/include/glib_compat.h
View file

@ -142,6 +142,7 @@ struct _GHashTableIter
void g_hash_table_destroy(GHashTable *hash_table);
gpointer g_hash_table_find(GHashTable *hash_table, GHRFunc predicate, gpointer user_data);
void g_hash_table_foreach(GHashTable *hash_table, GHFunc func, gpointer user_data);
GList *g_hash_table_get_keys(GHashTable *hash_table);
void g_hash_table_insert(GHashTable *hash_table, gpointer key, gpointer value);
void g_hash_table_replace(GHashTable *hash_table, gpointer key, gpointer value);
gpointer g_hash_table_lookup(GHashTable *hash_table, gconstpointer key);

30
qemu/target/arm/cpu.c
View file

@ -993,16 +993,12 @@ static void arm1026_initfn(struct uc_struct *uc, Object *obj, void *opaque)
{
/* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
ARMCPRegInfo ifar = { 0 };
ifar.name = "IFAR";
ifar.cp = 15;
ifar.crn = 6;
ifar.crm = 0;
ifar.opc1 = 0;
ifar.opc2 = 1;
ifar.access = PL1_RW;
ifar.fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
ifar.resetvalue = 0;
ARMCPRegInfo ifar = {
.name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
.access = PL1_RW,
.fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
.resetvalue = 0
};
define_one_arm_cp_reg(cpu, &ifar);
}
}
@ -1858,12 +1854,14 @@ static void arm_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data
static void cpu_register(struct uc_struct *uc, const ARMCPUInfo *info)
{
TypeInfo type_info = { 0 };
type_info.parent = TYPE_ARM_CPU;
type_info.instance_size = sizeof(ARMCPU);
type_info.instance_init = info->initfn;
type_info.class_size = sizeof(ARMCPUClass);
type_info.class_init = info->class_init;
TypeInfo type_info = {
.parent = TYPE_ARM_CPU,
.instance_size = sizeof(ARMCPU),
.instance_init = info->initfn,
.class_size = sizeof(ARMCPUClass),
.class_init = info->class_init,
.class_data = (void *)info,
};
type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
type_register(uc, &type_info);

14
qemu/target/arm/cpu64.c
View file

@ -373,12 +373,14 @@ static void aarch64_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *
static void aarch64_cpu_register(struct uc_struct *uc, const ARMCPUInfo *info)
{
TypeInfo type_info = { 0 };
type_info.parent = TYPE_AARCH64_CPU;
type_info.instance_size = sizeof(ARMCPU);
type_info.instance_init = info->initfn;
type_info.class_size = sizeof(ARMCPUClass);
type_info.class_init = info->class_init;
TypeInfo type_info = {
.parent = TYPE_AARCH64_CPU,
.instance_size = sizeof(ARMCPU),
.instance_init = info->initfn,
.class_size = sizeof(ARMCPUClass),
.class_init = info->class_init,
.class_data = (void *)info,
};
type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
type_register(uc, &type_info);

94
qemu/target/arm/translate.c
View file

@ -3129,22 +3129,9 @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
return 1;
}
// this causes "warning C4293: shift count negative or too big, undefined behavior"
// on msvc, so is replaced with separate versions for the shift to perform.
//#define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
#if 0
//#define VFP_SREG(insn, bigbit, smallbit) \
// ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
#endif
#define VFP_REG_SHR_NEG(insn, n) ((insn) << -(n))
#define VFP_SREG_NEG(insn, bigbit, smallbit) \
((VFP_REG_SHR_NEG(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
#define VFP_REG_SHR_POS(x, n) ((insn) >> (n))
#define VFP_SREG_POS(insn, bigbit, smallbit) \
((VFP_REG_SHR_POS(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
#define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
#define VFP_SREG(insn, bigbit, smallbit) \
((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
#define VFP_DREG(reg, insn, bigbit, smallbit) do { \
if (arm_dc_feature(s, ARM_FEATURE_VFP3)) { \
reg = (((insn) >> (bigbit)) & 0x0f) \
@ -3155,11 +3142,11 @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
reg = ((insn) >> (bigbit)) & 0x0f; \
}} while (0)
#define VFP_SREG_D(insn) VFP_SREG_POS(insn, 12, 22)
#define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
#define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
#define VFP_SREG_N(insn) VFP_SREG_POS(insn, 16, 7)
#define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
#define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
#define VFP_SREG_M(insn) VFP_SREG_NEG(insn, 0, 5)
#define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
#define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
/* Move between integer and VFP cores. */
@ -6131,17 +6118,20 @@ static void gen_shl64_ins_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, int64_t shi
static void gen_shl_ins_vec(TCGContext *s, unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh)
{
uint64_t mask = (1ull << sh) - 1;
TCGv_vec t = tcg_temp_new_vec_matching(s, d);
TCGv_vec m = tcg_temp_new_vec_matching(s, d);
if (sh == 0) {
tcg_gen_mov_vec(s, d, a);
} else {
TCGv_vec t = tcg_temp_new_vec_matching(s, d);
TCGv_vec m = tcg_temp_new_vec_matching(s, d);
tcg_gen_dupi_vec(s, vece, m, mask);
tcg_gen_shli_vec(s, vece, t, a, sh);
tcg_gen_and_vec(s, vece, d, d, m);
tcg_gen_or_vec(s, vece, d, d, t);
tcg_gen_dupi_vec(s, vece, m, MAKE_64BIT_MASK(0, sh));
tcg_gen_shli_vec(s, vece, t, a, sh);
tcg_gen_and_vec(s, vece, d, d, m);
tcg_gen_or_vec(s, vece, d, d, t);
tcg_temp_free_vec(s, t);
tcg_temp_free_vec(s, m);
tcg_temp_free_vec(s, t);
tcg_temp_free_vec(s, m);
}
}
const GVecGen2i sli_op[4] = {
@ -6174,54 +6164,54 @@ static void gen_mla8_i32(TCGContext *s, TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
gen_helper_neon_add_u8(s, d, d, a);
}
static void gen_mla16_i32(TCGContext *s, TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
{
gen_helper_neon_mul_u16(s, a, a, b);
gen_helper_neon_add_u16(s, d, d, a);
}
static void gen_mla32_i32(TCGContext *s, TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
{
tcg_gen_mul_i32(s, a, a, b);
tcg_gen_add_i32(s, d, d, a);
}
static void gen_mla64_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{
tcg_gen_mul_i64(s, a, a, b);
tcg_gen_add_i64(s, d, d, a);
}
static void gen_mla_vec(TCGContext *s, unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
{
tcg_gen_mul_vec(s, vece, a, a, b);
tcg_gen_add_vec(s, vece, d, d, a);
}
static void gen_mls8_i32(TCGContext *s, TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
{
gen_helper_neon_mul_u8(s, a, a, b);
gen_helper_neon_sub_u8(s, d, d, a);
}
static void gen_mla16_i32(TCGContext *s, TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
{
gen_helper_neon_mul_u16(s, a, a, b);
gen_helper_neon_add_u16(s, d, d, a);
}
static void gen_mls16_i32(TCGContext *s, TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
{
gen_helper_neon_mul_u16(s, a, a, b);
gen_helper_neon_sub_u16(s, d, d, a);
}
static void gen_mla32_i32(TCGContext *s, TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
{
tcg_gen_mul_i32(s, a, a, b);
tcg_gen_add_i32(s, d, d, a);
}
static void gen_mls32_i32(TCGContext *s, TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
{
tcg_gen_mul_i32(s, a, a, b);
tcg_gen_sub_i32(s, d, d, a);
}
static void gen_mla64_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{
tcg_gen_mul_i64(s, a, a, b);
tcg_gen_add_i64(s, d, d, a);
}
static void gen_mls64_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{
tcg_gen_mul_i64(s, a, a, b);
tcg_gen_sub_i64(s, d, d, a);
}
static void gen_mla_vec(TCGContext *s, unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
{
tcg_gen_mul_vec(s, vece, a, a, b);
tcg_gen_add_vec(s, vece, d, d, a);
}
static void gen_mls_vec(TCGContext *s, unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
{
tcg_gen_mul_vec(s, vece, a, a, b);