yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-02-02 14:51:04 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/arm: Split VMINMAXNM decode

Browse source 
Passing the raw op field from the manual is less instructive
than it might be. Do the full decode and use the existing
helpers to perform the expansion.

Since these are v8 insns, VECLEN+VECSTRIDE are already RES0.

Backports commit f2eafb75511e5d2ee601b43dc6ee0bcc6e453acd from qemu
This commit is contained in:
Richard Henderson 2020-03-22 00:09:51 -04:00 committed by Lioncash
parent 303d922e5d
commit c3eaaf7c33
2 changed files with 44 additions and 78 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

110
qemu/target/arm/translate-vfp.inc.c
View file

@ -326,80 +326,6 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
return true;
}
static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
uint32_t rd, rn, rm;
bool dp = a->dp;
bool vmin = a->op;
TCGv_ptr fpst;
if (!dc_isar_feature(aa32_vminmaxnm, s)) {
return false;
}
if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
/* UNDEF accesses to D16-D31 if they don't exist */
if (dp && !dc_isar_feature(aa32_simd_r32, s) &&
((a->vm | a->vn | a->vd) & 0x10)) {
return false;
}
rd = a->vd;
rn = a->vn;
rm = a->vm;
if (!vfp_access_check(s)) {
return true;
}
fpst = get_fpstatus_ptr(s, 0);
if (dp) {
TCGv_i64 frn, frm, dest;
frn = tcg_temp_new_i64(tcg_ctx);
frm = tcg_temp_new_i64(tcg_ctx);
dest = tcg_temp_new_i64(tcg_ctx);
neon_load_reg64(s, frn, rn);
neon_load_reg64(s, frm, rm);
if (vmin) {
gen_helper_vfp_minnumd(tcg_ctx, dest, frn, frm, fpst);
} else {
gen_helper_vfp_maxnumd(tcg_ctx, dest, frn, frm, fpst);
}
neon_store_reg64(s, dest, rd);
tcg_temp_free_i64(tcg_ctx, frn);
tcg_temp_free_i64(tcg_ctx, frm);
tcg_temp_free_i64(tcg_ctx, dest);
} else {
TCGv_i32 frn, frm, dest;
frn = tcg_temp_new_i32(tcg_ctx);
frm = tcg_temp_new_i32(tcg_ctx);
dest = tcg_temp_new_i32(tcg_ctx);
neon_load_reg32(s, frn, rn);
neon_load_reg32(s, frm, rm);
if (vmin) {
gen_helper_vfp_minnums(tcg_ctx, dest, frn, frm, fpst);
} else {
gen_helper_vfp_maxnums(tcg_ctx, dest, frn, frm, fpst);
}
neon_store_reg32(s, dest, rd);
tcg_temp_free_i32(tcg_ctx, frn);
tcg_temp_free_i32(tcg_ctx, frm);
tcg_temp_free_i32(tcg_ctx, dest);
}
tcg_temp_free_ptr(tcg_ctx, fpst);
return true;
}
/*
* Table for converting the most common AArch32 encoding of
* rounding mode to arm_fprounding order (which matches the
@ -1808,6 +1734,42 @@ static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_dp *a)
return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, false);
}
static bool trans_VMINNM_sp(DisasContext *s, arg_VMINNM_sp *a)
{
if (!dc_isar_feature(aa32_vminmaxnm, s)) {
return false;
}
return do_vfp_3op_sp(s, gen_helper_vfp_minnums,
a->vd, a->vn, a->vm, false);
}
static bool trans_VMAXNM_sp(DisasContext *s, arg_VMAXNM_sp *a)
{
if (!dc_isar_feature(aa32_vminmaxnm, s)) {
return false;
}
return do_vfp_3op_sp(s, gen_helper_vfp_maxnums,
a->vd, a->vn, a->vm, false);
}
static bool trans_VMINNM_dp(DisasContext *s, arg_VMINNM_dp *a)
{
if (!dc_isar_feature(aa32_vminmaxnm, s)) {
return false;
}
return do_vfp_3op_dp(s, gen_helper_vfp_minnumd,
a->vd, a->vn, a->vm, false);
}
static bool trans_VMAXNM_dp(DisasContext *s, arg_VMAXNM_dp *a)
{
if (!dc_isar_feature(aa32_vminmaxnm, s)) {
return false;
}
return do_vfp_3op_dp(s, gen_helper_vfp_maxnumd,
a->vd, a->vn, a->vm, false);
}
static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool neg_d)
{
/*

12
qemu/target/arm/vfp-uncond.decode
View file

@ -41,15 +41,19 @@
%vd_dp 22:1 12:4
%vd_sp 12:4 22:1
@vfp_dnm_s ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp
@vfp_dnm_d ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp
VSEL 1111 1110 0. cc:2 .... .... 1010 .0.0 .... \
vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0
VSEL 1111 1110 0. cc:2 .... .... 1011 .0.0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1
VMINMAXNM 1111 1110 1.00 .... .... 1010 . op:1 .0 .... \
vm=%vm_sp vn=%vn_sp vd=%vd_sp dp=0
VMINMAXNM 1111 1110 1.00 .... .... 1011 . op:1 .0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp dp=1
VMAXNM_sp 1111 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s
VMINNM_sp 1111 1110 1.00 .... .... 1010 .1.0 .... @vfp_dnm_s
VMAXNM_dp 1111 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d
VMINNM_dp 1111 1110 1.00 .... .... 1011 .1.0 .... @vfp_dnm_d
VRINT 1111 1110 1.11 10 rm:2 .... 1010 01.0 .... \
vm=%vm_sp vd=%vd_sp dp=0