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target/arm: Create new arm_v7m_mmu_idx_for_secstate_and_priv()
The TT instruction is going to need to look up the MMU index for a specified security and privilege state. Refactor the existing arm_v7m_mmu_idx_for_secstate() into a version that lets you specify the privilege state and one that uses the current state of the CPU. Backports commit ec8e3340286a87d3924c223d60ba5c994549f796 from qemu
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@ -2300,14 +2300,16 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
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}
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}
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/* Return the MMU index for a v7M CPU in the specified security state */
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static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env,
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bool secstate)
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/* Return the MMU index for a v7M CPU in the specified security and
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* privilege state
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*/
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static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
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bool secstate,
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bool priv)
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{
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int el = arm_current_el(env);
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ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
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if (el != 0) {
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if (priv) {
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mmu_idx |= ARM_MMU_IDX_M_PRIV;
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}
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@ -2325,6 +2327,15 @@ static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env,
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return mmu_idx;
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}
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/* Return the MMU index for a v7M CPU in the specified security state */
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static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env,
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bool secstate)
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{
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bool priv = arm_current_el(env) != 0;
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return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
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}
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/* Determine the current mmu_idx to use for normal loads/stores */
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static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
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{
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