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target/arm: Replace CPSR_ERET_MASK with aarch32_cpsr_valid_mask

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CPSR_ERET_MASK was a useless renaming of CPSR_RESERVED.
The function also takes into account bits that the cpu
does not support.

Backports commit 437864216d63f052f3cd06ec8861d0e432496424 from qemu
This commit is contained in:
Richard Henderson 2020-03-21 17:19:16 -04:00 committed by Lioncash
parent e4a7a089f0
commit c450694f1a
2 changed files with 4 additions and 3 deletions
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2
qemu/target/arm/cpu.h
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@ -1094,8 +1094,6 @@ void pmu_init(ARMCPU *cpu);
#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
/* Execution state bits. MRS read as zero, MSR writes ignored. */
#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
/* Mask of bits which may be set by exception return copying them from SPSR */
#define CPSR_ERET_MASK (~CPSR_RESERVED)
/* Bit definitions for M profile XPSR. Most are the same as CPSR. */
#define XPSR_EXCP 0x1ffU

5
qemu/target/arm/op_helper.c
View file

@ -405,9 +405,12 @@ void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
/* Write the CPSR for a 32-bit exception return */
void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val)
{
uint32_t mask;
arm_call_pre_el_change_hook(env_archcpu(env));
cpsr_write(env, val, CPSR_ERET_MASK, CPSRWriteExceptionReturn);
mask = aarch32_cpsr_valid_mask(env->features, &env_archcpu(env)->isar);
cpsr_write(env, val, mask, CPSRWriteExceptionReturn);
/*
* Generated code has already stored the new PC value, but