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target-sparc: Pass TCGMemOp to gen_ld/st_asi

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Backports commit 1d65b0f5bb8f32500bbce09d922d226bb7cf4c68 from qemu
This commit is contained in:
Richard Henderson 2018-02-25 17:26:30 -05:00 committed by Lioncash
parent 4bc53f223c
commit c509a5562d
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 16 additions and 16 deletions
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32
qemu/target-sparc/translate.c
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@ -2143,7 +2143,7 @@ static DisasASI get_asi(DisasContext *dc, int insn)
} }
static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
int insn, int size, int sign) int insn, TCGMemOp memop)
{ {
TCGContext *tcg_ctx = dc->uc->tcg_ctx; TCGContext *tcg_ctx = dc->uc->tcg_ctx;
DisasASI da = get_asi(dc, insn); DisasASI da = get_asi(dc, insn);
@ -2154,8 +2154,8 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
default: default:
{ {
TCGv_i32 r_asi = tcg_const_i32(tcg_ctx, da.asi); TCGv_i32 r_asi = tcg_const_i32(tcg_ctx, da.asi);
TCGv_i32 r_size = tcg_const_i32(tcg_ctx, size); TCGv_i32 r_size = tcg_const_i32(tcg_ctx, 1 << (memop & MO_SIZE));
TCGv_i32 r_sign = tcg_const_i32(tcg_ctx, sign); TCGv_i32 r_sign = tcg_const_i32(tcg_ctx, !!(memop & MO_SIGN));
save_state(dc); save_state(dc);
#ifdef TARGET_SPARC64 #ifdef TARGET_SPARC64
@ -2177,7 +2177,7 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
} }
static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
int insn, int size) int insn, TCGMemOp memop)
{ {
TCGContext *tcg_ctx = dc->uc->tcg_ctx; TCGContext *tcg_ctx = dc->uc->tcg_ctx;
DisasASI da = get_asi(dc, insn); DisasASI da = get_asi(dc, insn);
@ -2188,7 +2188,7 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
default: default:
{ {
TCGv_i32 r_asi = tcg_const_i32(tcg_ctx, da.asi); TCGv_i32 r_asi = tcg_const_i32(tcg_ctx, da.asi);
TCGv_i32 r_size = tcg_const_i32(tcg_ctx, size); TCGv_i32 r_size = tcg_const_i32(tcg_ctx, 1 << (memop & MO_SIZE));
save_state(dc); save_state(dc);
#ifdef TARGET_SPARC64 #ifdef TARGET_SPARC64
@ -4986,13 +4986,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
break; break;
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
case 0x10: /* lda, V9 lduwa, load word alternate */ case 0x10: /* lda, V9 lduwa, load word alternate */
gen_ld_asi(dc, cpu_val, cpu_addr, insn, 4, 0); gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL);
break; break;
case 0x11: /* lduba, load unsigned byte alternate */ case 0x11: /* lduba, load unsigned byte alternate */
gen_ld_asi(dc, cpu_val, cpu_addr, insn, 1, 0); gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_UB);
break; break;
case 0x12: /* lduha, load unsigned halfword alternate */ case 0x12: /* lduha, load unsigned halfword alternate */
gen_ld_asi(dc, cpu_val, cpu_addr, insn, 2, 0); gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW);
break; break;
case 0x13: /* ldda, load double word alternate */ case 0x13: /* ldda, load double word alternate */
if (rd & 1) { if (rd & 1) {
@ -5001,10 +5001,10 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
gen_ldda_asi(dc, cpu_val, cpu_addr, insn, rd); gen_ldda_asi(dc, cpu_val, cpu_addr, insn, rd);
goto skip_move; goto skip_move;
case 0x19: /* ldsba, load signed byte alternate */ case 0x19: /* ldsba, load signed byte alternate */
gen_ld_asi(dc, cpu_val, cpu_addr, insn, 1, 1); gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_SB);
break; break;
case 0x1a: /* ldsha, load signed halfword alternate */ case 0x1a: /* ldsha, load signed halfword alternate */
gen_ld_asi(dc, cpu_val, cpu_addr, insn, 2, 1); gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESW);
break; break;
case 0x1d: /* ldstuba -- XXX: should be atomically */ case 0x1d: /* ldstuba -- XXX: should be atomically */
gen_ldstub_asi(dc, cpu_val, cpu_addr, insn); gen_ldstub_asi(dc, cpu_val, cpu_addr, insn);
@ -5033,10 +5033,10 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
tcg_gen_qemu_ld64(dc->uc, cpu_val, cpu_addr, dc->mem_idx); tcg_gen_qemu_ld64(dc->uc, cpu_val, cpu_addr, dc->mem_idx);
break; break;
case 0x18: /* V9 ldswa */ case 0x18: /* V9 ldswa */
gen_ld_asi(dc, cpu_val, cpu_addr, insn, 4, 1); gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL);
break; break;
case 0x1b: /* V9 ldxa */ case 0x1b: /* V9 ldxa */
gen_ld_asi(dc, cpu_val, cpu_addr, insn, 8, 0); gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEQ);
break; break;
case 0x2d: /* V9 prefetch, no effect */ case 0x2d: /* V9 prefetch, no effect */
goto skip_move; goto skip_move;
@ -5168,13 +5168,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
break; break;
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
case 0x14: /* sta, V9 stwa, store word alternate */ case 0x14: /* sta, V9 stwa, store word alternate */
gen_st_asi(dc, cpu_val, cpu_addr, insn, 4); gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL);
break; break;
case 0x15: /* stba, store byte alternate */ case 0x15: /* stba, store byte alternate */
gen_st_asi(dc, cpu_val, cpu_addr, insn, 1); gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_UB);
break; break;
case 0x16: /* stha, store halfword alternate */ case 0x16: /* stha, store halfword alternate */
gen_st_asi(dc, cpu_val, cpu_addr, insn, 2); gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW);
break; break;
case 0x17: /* stda, store double word alternate */ case 0x17: /* stda, store double word alternate */
if (rd & 1) { if (rd & 1) {
@ -5189,7 +5189,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
tcg_gen_qemu_st64(dc->uc, cpu_val, cpu_addr, dc->mem_idx); tcg_gen_qemu_st64(dc->uc, cpu_val, cpu_addr, dc->mem_idx);
break; break;
case 0x1e: /* V9 stxa */ case 0x1e: /* V9 stxa */
gen_st_asi(dc, cpu_val, cpu_addr, insn, 8); gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEQ);
break; break;
#endif #endif
default: default: