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target/arm: Convert T16 one low register and immediate
Backports commit 6c6d237a865041972ec5b226657398f3b3018561 from qemu
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d9184b16a9
commit
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qemu/target/arm
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@ -133,3 +133,14 @@ SUB_rrri 0001101 ... ... ... @addsub_3
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ADD_rri 0001 110 ... ... ... @addsub_2i
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SUB_rri 0001 111 ... ... ... @addsub_2i
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# Add, subtract, compare, move (one low register and immediate)
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%reg_8 8:3
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@arith_1i ..... rd:3 imm:8 \
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&s_rri_rot rot=0 rn=%reg_8
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MOV_rxi 00100 ... ........ @arith_1i %s
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CMP_xri 00101 ... ........ @arith_1i s=1
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ADD_rri 00110 ... ........ @arith_1i %s
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SUB_rri 00111 ... ........ @arith_1i %s
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@ -11057,48 +11057,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
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store_reg(s, rd, tmp);
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}
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break;
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case 2: case 3:
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/*
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* 0b001x_xxxx_xxxx_xxxx
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* - Add, subtract, compare, move (one low register and immediate)
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*/
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op = (insn >> 11) & 3;
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rd = (insn >> 8) & 0x7;
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if (op == 0) { /* mov */
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tmp = tcg_temp_new_i32(tcg_ctx);
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tcg_gen_movi_i32(tcg_ctx, tmp, insn & 0xff);
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if (!s->condexec_mask)
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gen_logic_CC(s, tmp);
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store_reg(s, rd, tmp);
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} else {
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tmp = load_reg(s, rd);
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tmp2 = tcg_temp_new_i32(tcg_ctx);
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tcg_gen_movi_i32(tcg_ctx, tmp2, insn & 0xff);
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switch (op) {
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case 1: /* cmp */
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gen_sub_CC(s, tmp, tmp, tmp2);
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tcg_temp_free_i32(tcg_ctx, tmp);
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tcg_temp_free_i32(tcg_ctx, tmp2);
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break;
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case 2: /* add */
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if (s->condexec_mask)
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tcg_gen_add_i32(tcg_ctx, tmp, tmp, tmp2);
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else
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gen_add_CC(s, tmp, tmp, tmp2);
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tcg_temp_free_i32(tcg_ctx, tmp2);
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store_reg(s, rd, tmp);
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break;
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case 3: /* sub */
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if (s->condexec_mask)
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tcg_gen_sub_i32(tcg_ctx, tmp, tmp, tmp2);
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else
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gen_sub_CC(s, tmp, tmp, tmp2);
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tcg_temp_free_i32(tcg_ctx, tmp2);
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store_reg(s, rd, tmp);
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break;
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}
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}
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break;
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case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */
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goto illegal_op;
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case 4:
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if (insn & (1 << 11)) {
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rd = (insn >> 8) & 7;
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