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arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16

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This includes FMAXNMP, FADDP, FMAXP, FMINNMP, FMINP.

Backports commit 7a2c6e618156674cf9eac8bf36e79f674fbf974e from qemu
This commit is contained in:
Alex Bennée 2018-03-08 15:50:52 -05:00 committed by Lioncash
parent 4b2577537b
commit c6fda07628
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 132 additions and 75 deletions
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57
qemu/target/arm/translate-a64.c
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@ -10399,6 +10399,7 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
int datasize, elements; int datasize, elements;
int pass; int pass;
TCGv_ptr fpst; TCGv_ptr fpst;
bool pairwise = false;
if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) { if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
unallocated_encoding(s); unallocated_encoding(s);
@ -10424,8 +10425,63 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
datasize = is_q ? 128 : 64; datasize = is_q ? 128 : 64;
elements = datasize / 16; elements = datasize / 16;
switch (fpopcode) {
case 0x10: /* FMAXNMP */
case 0x12: /* FADDP */
case 0x16: /* FMAXP */
case 0x18: /* FMINNMP */
case 0x1e: /* FMINP */
pairwise = true;
break;
}
fpst = get_fpstatus_ptr(tcg_ctx, true); fpst = get_fpstatus_ptr(tcg_ctx, true);
if (pairwise) {
int maxpass = is_q ? 8 : 4;
TCGv_i32 tcg_op1 = tcg_temp_new_i32(tcg_ctx);
TCGv_i32 tcg_op2 = tcg_temp_new_i32(tcg_ctx);
TCGv_i32 tcg_res[8];
for (pass = 0; pass < maxpass; pass++) {
int passreg = pass < (maxpass / 2) ? rn : rm;
int passelt = (pass << 1) & (maxpass - 1);
read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_16);
read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_16);
tcg_res[pass] = tcg_temp_new_i32(tcg_ctx);
switch (fpopcode) {
case 0x10: /* FMAXNMP */
gen_helper_advsimd_maxnumh(tcg_ctx, tcg_res[pass], tcg_op1, tcg_op2,
fpst);
break;
case 0x12: /* FADDP */
gen_helper_advsimd_addh(tcg_ctx, tcg_res[pass], tcg_op1, tcg_op2, fpst);
break;
case 0x16: /* FMAXP */
gen_helper_advsimd_maxh(tcg_ctx, tcg_res[pass], tcg_op1, tcg_op2, fpst);
break;
case 0x18: /* FMINNMP */
gen_helper_advsimd_minnumh(tcg_ctx, tcg_res[pass], tcg_op1, tcg_op2,
fpst);
break;
case 0x1e: /* FMINP */
gen_helper_advsimd_minh(tcg_ctx, tcg_res[pass], tcg_op1, tcg_op2, fpst);
break;
default:
g_assert_not_reached();
}
}
for (pass = 0; pass < maxpass; pass++) {
write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_16);
tcg_temp_free_i32(tcg_ctx, tcg_res[pass]);
}
tcg_temp_free_i32(tcg_ctx, tcg_op1);
tcg_temp_free_i32(tcg_ctx, tcg_op2);
} else {
for (pass = 0; pass < elements; pass++) { for (pass = 0; pass < elements; pass++) {
TCGv_i32 tcg_op1 = tcg_temp_new_i32(tcg_ctx); TCGv_i32 tcg_op1 = tcg_temp_new_i32(tcg_ctx);
TCGv_i32 tcg_op2 = tcg_temp_new_i32(tcg_ctx); TCGv_i32 tcg_op2 = tcg_temp_new_i32(tcg_ctx);
@ -10510,6 +10566,7 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
tcg_temp_free_i32(tcg_ctx, tcg_op1); tcg_temp_free_i32(tcg_ctx, tcg_op1);
tcg_temp_free_i32(tcg_ctx, tcg_op2); tcg_temp_free_i32(tcg_ctx, tcg_op2);
} }
}
tcg_temp_free_ptr(tcg_ctx, fpst); tcg_temp_free_ptr(tcg_ctx, fpst);