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target-arm: Add VBAR support to ARM1176 CPUs

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ARM1176 CPUs have TrustZone support and can use the Vector Base
Address Register, but currently, qemu only adds VBAR support to ARMv7
CPUs. Fix this by adding a new feature ARM_FEATURE_VBAR which can used
for ARMv7 and ARM1176 CPUs.

The VBAR feature is always set for ARMv7 because some legacy boards
require it even if this is not architecturally correct.

Backports commit 91db4642f868cf2e591b62d31a19d35b02ea791e from qemu
This commit is contained in:
Cédric Le Goater 2018-03-01 11:12:23 -05:00 committed by Lioncash
parent 554ad1f34e
commit c7ab1e782b
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 12 additions and 4 deletions
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16
qemu/target-arm/helper.c
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@ -1105,10 +1105,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
{ "PMINTENCLR_EL1", 0,9,14, 3,0,2, ARM_CP_STATE_AA64, ARM_CP_ALIAS, { "PMINTENCLR_EL1", 0,9,14, 3,0,2, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten), {0, 0}, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten), {0, 0},
access_tpm, NULL, pmintenclr_write }, access_tpm, NULL, pmintenclr_write },
{ "VBAR", 0,12,0, 3,0,0, ARM_CP_STATE_BOTH, 0,
PL1_RW, 0, NULL, 0, 0,
{ offsetof(CPUARMState, cp15.vbar_s), offsetof(CPUARMState, cp15.vbar_ns) },
NULL, NULL, vbar_write, },
{ "CCSIDR", 0,0,0, 3,1,0, ARM_CP_STATE_BOTH, { "CCSIDR", 0,0,0, 3,1,0, ARM_CP_STATE_BOTH,
ARM_CP_NO_RAW, PL1_R, 0, NULL, 0, 0, {0, 0}, ARM_CP_NO_RAW, PL1_R, 0, NULL, 0, 0, {0, 0},
NULL, ccsidr_read, }, NULL, ccsidr_read, },
@ -4386,6 +4382,18 @@ void register_cp_regs_for_features(ARMCPU *cpu)
} }
} }
if (arm_feature(env, ARM_FEATURE_VBAR)) {
ARMCPRegInfo vbar_cp_reginfo[] = {
{ "VBAR", 0,12,0, 3,0,0, ARM_CP_STATE_BOTH, 0,
PL1_RW, 0, NULL, 0, 0,
{ offsetof(CPUARMState, cp15.vbar_s),
offsetof(CPUARMState, cp15.vbar_ns) },
NULL, NULL, vbar_write },
REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, vbar_cp_reginfo);
}
/* Generic registers whose values depend on the implementation */ /* Generic registers whose values depend on the implementation */
{ {
ARMCPRegInfo sctlr = { ARMCPRegInfo sctlr = {