target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0

This commit doesn't add any supported events, but provides the framework
for adding them. We store the pm_event structs in a simple array, and
provide the mapping from the event numbers to array indexes in the
supported_event_map array. Because the value of PMCEID[01] depends upon
which events are supported at runtime, generate it dynamically.

Backports commit 57a4a11b2b281bb548b419ca81bfafb214e4c77a from qemu
This commit is contained in:
Aaron Lindsay 2019-01-22 17:38:07 -05:00 committed by Lioncash
parent 67accd4d88
commit c8c3defb18
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
9 changed files with 85 additions and 13 deletions

View file

@ -3301,6 +3301,7 @@
#define fp_exception_el fp_exception_el_aarch64
#define gen_a64_set_pc_im gen_a64_set_pc_im_aarch64
#define gen_cmtst_i64 gen_cmtst_i64_aarch64
#define get_pmceid get_pmceid_aarch64
#define helper_advsimd_acge_f16 helper_advsimd_acge_f16_aarch64
#define helper_advsimd_acgt_f16 helper_advsimd_acgt_f16_aarch64
#define helper_advsimd_add2h helper_advsimd_add2h_aarch64

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@ -3301,6 +3301,7 @@
#define fp_exception_el fp_exception_el_aarch64eb
#define gen_a64_set_pc_im gen_a64_set_pc_im_aarch64eb
#define gen_cmtst_i64 gen_cmtst_i64_aarch64eb
#define get_pmceid get_pmceid_aarch64eb
#define helper_advsimd_acge_f16 helper_advsimd_acge_f16_aarch64eb
#define helper_advsimd_acgt_f16 helper_advsimd_acgt_f16_aarch64eb
#define helper_advsimd_add2h helper_advsimd_add2h_aarch64eb

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@ -3286,6 +3286,7 @@
#define cmtst_op cmtst_op_arm
#define fp_exception_el fp_exception_el_arm
#define gen_cmtst_i64 gen_cmtst_i64_arm
#define get_pmceid get_pmceid_arm
#define mla_op mla_op_arm
#define mls_op mls_op_arm
#define pmccntr_op_start pmccntr_op_start_arm

View file

@ -3286,6 +3286,7 @@
#define cmtst_op cmtst_op_armeb
#define fp_exception_el fp_exception_el_armeb
#define gen_cmtst_i64 gen_cmtst_i64_armeb
#define get_pmceid get_pmceid_armeb
#define mla_op mla_op_armeb
#define mls_op mls_op_armeb
#define pmccntr_op_start pmccntr_op_start_armeb

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@ -3295,6 +3295,7 @@ arm_symbols = (
'cmtst_op',
'fp_exception_el',
'gen_cmtst_i64',
'get_pmceid',
'mla_op',
'mls_op',
'pmccntr_op_start',
@ -3346,6 +3347,7 @@ aarch64_symbols = (
'fp_exception_el',
'gen_a64_set_pc_im',
'gen_cmtst_i64',
'get_pmceid',
'helper_advsimd_acge_f16',
'helper_advsimd_acgt_f16',
'helper_advsimd_add2h',

View file

@ -761,15 +761,19 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
if (!cpu->has_pmu) {
unset_feature(env, ARM_FEATURE_PMU);
cpu->id_aa64dfr0 &= ~0xf00;
}
// Unicorn: Commented out
#if 0
else if (!kvm_enabled()) {
if (arm_feature(env, ARM_FEATURE_PMU)) {
cpu->pmceid0 = get_pmceid(&cpu->env, 0);
cpu->pmceid1 = get_pmceid(&cpu->env, 1);
arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
} else {
cpu->id_aa64dfr0 &= ~0xf00;
cpu->pmceid0 = 0;
cpu->pmceid1 = 0;
}
#endif
if (!arm_feature(env, ARM_FEATURE_EL2)) {
/* Disable the hypervisor feature bits in the processor feature
@ -1410,8 +1414,6 @@ static void cortex_a7_initfn(struct uc_struct *uc, Object *obj, void *opaque)
cpu->id_pfr0 = 0x00001131;
cpu->id_pfr1 = 0x00011011;
cpu->id_dfr0 = 0x02010555;
cpu->pmceid0 = 0x00000000;
cpu->pmceid1 = 0x00000000;
cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x10101105;
cpu->id_mmfr1 = 0x40000000;
@ -1457,8 +1459,6 @@ static void cortex_a15_initfn(struct uc_struct *uc, Object *obj, void *opaque)
cpu->id_pfr0 = 0x00001131;
cpu->id_pfr1 = 0x00011011;
cpu->id_dfr0 = 0x02010555;
cpu->pmceid0 = 0x00000000;
cpu->pmceid1 = 0x00000000;
cpu->id_afr0 = 0x00000000;
cpu->id_mmfr0 = 0x10201105;
cpu->id_mmfr1 = 0x20000000;

View file

@ -671,6 +671,17 @@ typedef struct CPUARMState {
/* Store GICv3CPUState to access from this struct */
void *gicv3state;
// Note: The event map has been moved here in Unicorn to avoid non-const file-static state.
/*
* Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
* events (i.e. the statistical profiling extension), this implementation
* should first be updated to something sparse instead of the current
* supported_event_map[] array.
*/
#define MAX_EVENT_ID 0x0
uint16_t supported_event_map[MAX_EVENT_ID + 1];
// Unicorn engine
struct uc_struct *uc;
} CPUARMState;
@ -949,6 +960,16 @@ void pmu_op_finish(CPUARMState *env);
void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
void pmu_post_el_change(ARMCPU *cpu, void *ignored);
/*
* get_pmceid
* @env: CPUARMState
* @which: which PMCEID register to return (0 or 1)
*
* Return the PMCEID[01]_EL0 register values corresponding to the counters
* which are supported given the current configuration
*/
uint64_t get_pmceid(CPUARMState *env, unsigned which);
/* SCTLR bit meanings. Several bits have been reused in newer
* versions of the architecture; in that case we define constants
* for both old and new bit meanings. Code which tests against those

View file

@ -118,8 +118,6 @@ static void aarch64_a57_initfn(struct uc_struct *uc, Object *obj, void *opaque)
cpu->isar.id_isar6 = 0;
cpu->isar.id_aa64pfr0 = 0x00002222;
cpu->id_aa64dfr0 = 0x10305106;
cpu->pmceid0 = 0x00000000;
cpu->pmceid1 = 0x00000000;
cpu->isar.id_aa64isar0 = 0x00011120;
cpu->isar.id_aa64mmfr0 = 0x00001124;
cpu->dbgdidr = 0x3516d000;
@ -220,8 +218,6 @@ static void aarch64_a72_initfn(struct uc_struct *uc, Object *obj, void *opaque)
cpu->isar.id_isar5 = 0x00011121;
cpu->isar.id_aa64pfr0 = 0x00002222;
cpu->id_aa64dfr0 = 0x10305106;
cpu->pmceid0 = 0x00000000;
cpu->pmceid1 = 0x00000000;
cpu->isar.id_aa64isar0 = 0x00011120;
cpu->isar.id_aa64mmfr0 = 0x00001124;
cpu->dbgdidr = 0x3516d000;

View file

@ -873,6 +873,55 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);
}
typedef struct pm_event {
uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */
/* If the event is supported on this CPU (used to generate PMCEID[01]) */
bool (*supported)(CPUARMState *);
/*
* Retrieve the current count of the underlying event. The programmed
* counters hold a difference from the return value from this function
*/
uint64_t (*get_count)(CPUARMState *);
} pm_event;
static const pm_event pm_events[] = {
};
#define UNSUPPORTED_EVENT UINT16_MAX
/*
* Called upon initialization to build PMCEID0_EL0 or PMCEID1_EL0 (indicated by
* 'which'). We also use it to build a map of ARM event numbers to indices in
* our pm_events array.
*
* Note: Events in the 0x40XX range are not currently supported.
*/
uint64_t get_pmceid(CPUARMState *env, unsigned which)
{
uint64_t pmceid = 0;
unsigned int i;
assert(which <= 1);
for (i = 0; i < ARRAY_SIZE(env->supported_event_map); i++) {
env->supported_event_map[i] = UNSUPPORTED_EVENT;
}
for (i = 0; i < ARRAY_SIZE(pm_events); i++) {
const pm_event *cnt = &pm_events[i];
assert(cnt->number <= MAX_EVENT_ID);
/* We do not currently support events in the 0x40xx range */
assert(cnt->number <= 0x3f);
if ((cnt->number & 0x20) == (which << 6) &&
cnt->supported(env)) {
pmceid |= (1 << (cnt->number & 0x1f));
env->supported_event_map[cnt->number] = i;
}
}
return pmceid;
}
static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{