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https://github.com/yuzu-emu/unicorn.git
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target/arm/helper: Correct bad merge
This commit is contained in:
Lioncash
parent
14c1fcd5bf
commit
c93c3bd4b3
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@ -1989,7 +1989,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
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/* We do not set any attribute bits in the PAR */
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if (page_size == (1 << 24)
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&& arm_feature(env, ARM_FEATURE_V7)) {
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par64 = (phys_addr & 0xff000000) | 1 << 1;
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par64 = (phys_addr & 0xff000000) | (1 << 1);
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} else {
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par64 = phys_addr & 0xfffff000;
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}
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@ -2310,7 +2310,7 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
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}
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}
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/* Update the masks corresponding to the the TCR bank being written
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/* Update the masks corresponding to the TCR bank being written
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* Note that we always calculate mask and base_mask, but
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* they are only used for short-descriptor tables (ie if EAE is 0);
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* for long-descriptor tables the TCR fields are used differently
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@ -2608,7 +2608,6 @@ static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
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return env->cp15.vmpidr_el2;
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}
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return mpidr_read_val(env);
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}
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@ -2732,13 +2731,12 @@ static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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}
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static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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uint64_t value)
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{
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/* Note that the 'ALL' scope must invalidate both stage 1 and
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* stage 2 translations, whereas most other scopes only invalidate
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* stage 1 translations.
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*/
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ARMCPU *cpu = arm_env_get_cpu(env);
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CPUState *cs = CPU(cpu);
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@ -4256,10 +4254,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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define_arm_cp_regs(cpu, v7mp_cp_reginfo);
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}
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if (arm_feature(env, ARM_FEATURE_V7)) {
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ARMCPRegInfo clidr = {
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"CLIDR", 0,0,0, 3,1,1, ARM_CP_STATE_BOTH,
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ARM_CP_CONST, PL1_R, 0, NULL, cpu->clidr
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};
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/* v7 performance monitor control register: same implementor
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* field as main ID register, and we implement only the cycle
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* count register.
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@ -4278,6 +4272,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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define_one_arm_cp_reg(cpu, &pmcr);
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define_one_arm_cp_reg(cpu, &pmcr64);
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#endif
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ARMCPRegInfo clidr = {
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"CLIDR", 0,0,0, 3,1,1, ARM_CP_STATE_BOTH,
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ARM_CP_CONST, PL1_R, 0, NULL, cpu->clidr
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};
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define_one_arm_cp_reg(cpu, &clidr);
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define_arm_cp_regs(cpu, v7_cp_reginfo);
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define_debug_regs(cpu);
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@ -4600,6 +4598,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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ARM_CP_CONST, PL1_R, 0, NULL, 0 },
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REGINFO_SENTINEL
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};
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/* TLBTR is specific to VMSA */
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ARMCPRegInfo id_tlbtr_reginfo = {
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"TLBTR", 15,0,0, 0,0,3, 0,
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ARM_CP_CONST, PL1_R, 0, NULL, 0,
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@ -4818,6 +4817,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
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* necessary as the register may have been defined with both states.
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*/
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r2->secure = secstate;
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if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
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/* Register is banked (using both entries in array).
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* Overwriting fieldoffset as the array is only used to define
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@ -4863,7 +4863,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
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#endif
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}
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}
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if (state == ARM_CP_STATE_AA64) {
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/* To allow abbreviation of ARMCPRegInfo
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* definitions, we treat cp == 0 as equivalent to
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@ -5679,6 +5678,7 @@ static void write_v7m_control_spsel_for_secstate(CPUARMState *env,
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if (secstate == env->v7m.secure) {
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bool new_is_psp = v7m_using_psp(env);
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uint32_t tmp;
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if (old_is_psp != new_is_psp) {
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tmp = env->v7m.other_sp;
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env->v7m.other_sp = env->regs[13];
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@ -6128,6 +6128,7 @@ static bool v7m_push_stack(ARMCPU *cpu)
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frameptr -= 4;
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xpsr |= XPSR_SPREALIGN;
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}
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frameptr -= 0x20;
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/* Write as much of the stack frame as we can. If we fail a stack
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@ -6160,7 +6161,6 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
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CPUState *cs = CPU(cpu);
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uint32_t excret;
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uint32_t xpsr;
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bool ufault = false;
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bool sfault = false;
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bool return_to_sp_process;
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@ -6486,6 +6486,79 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
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qemu_log_mask(CPU_LOG_INT, "...successful exception return\n");
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}
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static bool do_v7m_function_return(ARMCPU *cpu)
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{
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/* v8M security extensions magic function return.
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* We may either:
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* (1) throw an exception (longjump)
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* (2) return true if we successfully handled the function return
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* (3) return false if we failed a consistency check and have
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* pended a UsageFault that needs to be taken now
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*
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* At this point the magic return value is split between env->regs[15]
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* and env->thumb. We don't bother to reconstitute it because we don't
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* need it (all values are handled the same way).
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*/
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CPUARMState *env = &cpu->env;
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uint32_t newpc, newpsr, newpsr_exc;
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qemu_log_mask(CPU_LOG_INT, "...really v7M secure function return\n");
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{
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bool threadmode, spsel;
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TCGMemOpIdx oi;
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ARMMMUIdx mmu_idx;
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uint32_t *frame_sp_p;
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uint32_t frameptr;
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/* Pull the return address and IPSR from the Secure stack */
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threadmode = !arm_v7m_is_handler_mode(env);
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spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK;
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frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel);
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frameptr = *frame_sp_p;
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/* These loads may throw an exception (for MPU faults). We want to
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* do them as secure, so work out what MMU index that is.
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*/
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mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true);
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oi = make_memop_idx(MO_LE, arm_to_core_mmu_idx(mmu_idx));
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newpc = helper_le_ldul_mmu(env, frameptr, oi, 0);
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newpsr = helper_le_ldul_mmu(env, frameptr + 4, oi, 0);
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/* Consistency checks on new IPSR */
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newpsr_exc = newpsr & XPSR_EXCP;
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if (!((env->v7m.exception == 0 && newpsr_exc == 0) ||
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(env->v7m.exception == 1 && newpsr_exc != 0))) {
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/* Pend the fault and tell our caller to take it */
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env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;
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// Unicorn: commented out
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//armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
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// env->v7m.secure);
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qemu_log_mask(CPU_LOG_INT,
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"...taking INVPC UsageFault: "
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"IPSR consistency check failed\n");
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return false;
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}
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*frame_sp_p = frameptr + 8;
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}
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/* This invalidates frame_sp_p */
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switch_v7m_security_state(env, true);
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env->v7m.exception = newpsr_exc;
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env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK;
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if (newpsr & XPSR_SFPA) {
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env->v7m.control[M_REG_S] |= R_V7M_CONTROL_SFPA_MASK;
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}
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xpsr_write(env, 0, XPSR_IT);
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env->thumb = newpc & 1;
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env->regs[15] = newpc & ~1;
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qemu_log_mask(CPU_LOG_INT, "...function return successful\n");
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return true;
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}
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static void arm_log_exception(int idx)
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{
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if (qemu_loglevel_mask(CPU_LOG_INT)) {
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@ -6780,8 +6853,18 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
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case EXCP_IRQ:
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break;
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case EXCP_EXCEPTION_EXIT:
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do_v7m_exception_exit(cpu);
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return;
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if (env->regs[15] < EXC_RETURN_MIN_MAGIC) {
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/* Must be v8M security extension function return */
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assert(env->regs[15] >= FNC_RETURN_MIN_MAGIC);
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assert(arm_feature(env, ARM_FEATURE_M_SECURITY));
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if (do_v7m_function_return(cpu)) {
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return;
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}
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} else {
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do_v7m_exception_exit(cpu);
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return;
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}
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break;
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default:
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cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
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return; /* Never happens. Keep compiler happy. */
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@ -7124,11 +7207,11 @@ static void arm_cpu_do_interrupt_aarch32_(CPUState *cs)
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addr = 0x1c;
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/* Disable FIQ, IRQ and imprecise data aborts. */
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mask = CPSR_A | CPSR_I | CPSR_F;
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offset = 4;
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if (env->cp15.scr_el3 & SCR_FIQ) {
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/* FIQ routed to monitor mode */
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new_mode = ARM_CPU_MODE_MON;
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}
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offset = 4;
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break;
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case EXCP_VIRQ:
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new_mode = ARM_CPU_MODE_IRQ;
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@ -7154,7 +7237,7 @@ static void arm_cpu_do_interrupt_aarch32_(CPUState *cs)
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cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
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return; /* Never happens. Keep compiler happy. */
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}
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/* High vectors. */
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if (new_mode == ARM_CPU_MODE_MON) {
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addr += env->cp15.mvbar;
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} else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
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@ -7186,7 +7269,7 @@ static void arm_cpu_do_interrupt_aarch32_(CPUState *cs)
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/* Set new mode endianness */
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env->uncached_cpsr &= ~CPSR_E;
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if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) {
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env->uncached_cpsr |= ~CPSR_E;
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env->uncached_cpsr |= CPSR_E;
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}
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env->daif |= mask;
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/* this is a lie, as the was no c1_sys on V4T/V5, but who cares
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@ -7323,9 +7406,9 @@ static inline bool check_for_semihosting(CPUState *cs)
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} else {
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uint32_t imm;
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/* Only intercept calls from privileged modes, to provide some
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* semblance of security.
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*/
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/* Only intercept calls from privileged modes, to provide some
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* semblance of security.
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*/
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if (cs->exception_index != EXCP_SEMIHOST &&
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(!semihosting_enabled() ||
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((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR))) {
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@ -7340,7 +7423,7 @@ static inline bool check_for_semihosting(CPUState *cs)
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*/
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break;
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case EXCP_SWI:
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/* Check for semihosting interrupt. */
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/* Check for semihosting interrupt. */
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if (env->thumb) {
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imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env))
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& 0xff;
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@ -7356,7 +7439,7 @@ static inline bool check_for_semihosting(CPUState *cs)
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}
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return false;
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case EXCP_BKPT:
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/* See if this is a semihosting syscall. */
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/* See if this is a semihosting syscall. */
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if (env->thumb) {
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imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env))
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& 0xff;
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@ -7665,7 +7748,7 @@ static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
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case 6:
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return PAGE_READ;
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case 7:
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if (!arm_feature (env, ARM_FEATURE_V6K)) {
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if (!arm_feature(env, ARM_FEATURE_V6K)) {
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return 0;
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}
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return PAGE_READ;
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@ -8162,7 +8245,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
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if (arm_feature(env, ARM_FEATURE_V6K) &&
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(regime_sctlr(env, mmu_idx) & SCTLR_AFE)) {
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/* The simplified model uses AP[0] as an access control bit. */
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/* The simplified model uses AP[0] as an access control bit. */
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if ((ap & 1) == 0) {
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/* Access flag fault. */
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fi->type = ARMFault_AccessFlag;
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@ -8390,7 +8473,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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* is unpredictable. Flag this as a guest error. */
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if (sign != sext) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"AArch32: VTCR.S / VTCR.T0SZ[3] missmatch\n");
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"AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
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}
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}
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t1sz = extract32(tcr->raw_tcr, 16, 6);
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@ -8537,6 +8620,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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if (fi->type != ARMFault_None) {
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goto do_fault;
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}
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if (!(descriptor & 1) ||
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(!(descriptor & 2) && (level == 3))) {
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/* Invalid, or the Reserved level 3 encoding */
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@ -8564,14 +8648,14 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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/* Extract attributes from the descriptor */
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attrs = extract64(descriptor, 2, 10)
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| (extract64(descriptor, 52, 12) << 10);
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attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
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attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
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if (mmu_idx == ARMMMUIdx_S2NS) {
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/* Stage 2 table descriptors do not include any attribute fields */
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break;
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}
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/* Merge in attributes from table descriptors */
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attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
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attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
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/* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
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* means "force PL1 access only", which means forcing AP[1] to 0.
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*/
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@ -8604,7 +8688,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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fault_type = ARMFault_Permission;
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if (!(*prot & (1 << access_type))) {
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/* Unprivileged access not enabled */
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goto do_fault;
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}
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@ -8637,6 +8720,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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do_fault:
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fi->type = fault_type;
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fi->level = level;
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/* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
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fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS);
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return true;
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}
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@ -8985,7 +9070,6 @@ static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
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*phys_ptr = address;
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*prot = 0;
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if (mregion) {
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*mregion = -1;
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}
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@ -9087,6 +9171,7 @@ static bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
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return !(*prot & (1 << access_type));
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}
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static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, MemTxAttrs *txattrs,
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@ -9171,7 +9256,6 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
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return false;
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}
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*phys_ptr = address;
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for (n = 7; n >= 0; n--) {
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base = env->cp15.c6_region[n];
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@ -9326,6 +9410,7 @@ static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2)
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return ret;
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}
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/* get_phys_addr - get the physical address for this virtual address
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*
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* Find the physical address corresponding to the given virtual address,
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@ -9423,6 +9508,7 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
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if (arm_feature(env, ARM_FEATURE_PMSA)) {
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bool ret;
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*page_size = TARGET_PAGE_SIZE;
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if (arm_feature(env, ARM_FEATURE_V8)) {
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/* PMSAv8 */
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ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx,
|
||||
|
|
@ -9647,7 +9733,6 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
|
|||
return env->v7m.faultmask[env->v7m.secure];
|
||||
default:
|
||||
bad_reg:
|
||||
/* ??? For debugging only. */
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special"
|
||||
" register %d\n", reg);
|
||||
return 0;
|
||||
|
|
@ -9812,13 +9897,13 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
|
|||
env->v7m.faultmask[env->v7m.secure] = val & 1;
|
||||
break;
|
||||
case 20: /* CONTROL */
|
||||
/* Writing to the SPSEL bit only has an effect if we are in
|
||||
* thread mode; other bits can be updated by any privileged code.
|
||||
* write_v7m_control_spsel() deals with updating the SPSEL bit in
|
||||
* env->v7m.control, so we only need update the others.
|
||||
* For v7M, we must just ignore explicit writes to SPSEL in handler
|
||||
* mode; for v8M the write is permitted but will have no effect.
|
||||
*/
|
||||
/* Writing to the SPSEL bit only has an effect if we are in
|
||||
* thread mode; other bits can be updated by any privileged code.
|
||||
* write_v7m_control_spsel() deals with updating the SPSEL bit in
|
||||
* env->v7m.control, so we only need update the others.
|
||||
* For v7M, we must just ignore explicit writes to SPSEL in handler
|
||||
* mode; for v8M the write is permitted but will have no effect.
|
||||
*/
|
||||
if (arm_feature(env, ARM_FEATURE_V8) ||
|
||||
!arm_v7m_is_handler_mode(env)) {
|
||||
write_v7m_control_spsel(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0);
|
||||
|
|
@ -10951,6 +11036,7 @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)
|
|||
/* The algorithm that must be used to calculate the estimate
|
||||
* is specified by the ARM ARM.
|
||||
*/
|
||||
|
||||
static int do_recip_sqrt_estimate(int a)
|
||||
{
|
||||
int b, estimate;
|
||||
|
|
@ -10972,6 +11058,7 @@ static int do_recip_sqrt_estimate(int a)
|
|||
return estimate;
|
||||
}
|
||||
|
||||
|
||||
static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
|
||||
{
|
||||
int estimate;
|
||||
|
|
@ -10984,6 +11071,7 @@ static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
|
|||
}
|
||||
frac = extract64(frac, 0, 51) << 1;
|
||||
}
|
||||
|
||||
if (*exp & 1) {
|
||||
/* scaled = UInt('01':fraction<51:45>) */
|
||||
scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7));
|
||||
|
|
@ -11380,7 +11468,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
|
|||
flags |= ARM_TBFLAG_VFPEN_MASK;
|
||||
}
|
||||
flags |= (extract32(env->cp15.c15_cpar, 0, 2)
|
||||
<< ARM_TBFLAG_XSCALE_CPAR_SHIFT);
|
||||
<< ARM_TBFLAG_XSCALE_CPAR_SHIFT);
|
||||
}
|
||||
|
||||
flags |= (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT);
|
||||
|
|
|
|||
Loading…
Reference in a new issue