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target-arm: add MVBAR support
Use MVBAR register as exception vector base address for exceptions taken to CPU monitor mode. Backports commit e89e51a17ea0d8aef9bf9b766c98f963e835fbf2 from qemu
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@ -213,6 +213,7 @@ typedef struct CPUARMState {
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uint32_t c9_pminten; /* perf monitor interrupt enables */
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uint64_t mair_el1;
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uint64_t vbar_el[4]; /* vector base address register */
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uint32_t mvbar; /* (monitor) vector base address register */
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uint32_t c13_fcse; /* FCSE PID. */
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uint64_t contextidr_el1; /* Context ID. */
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uint64_t tpidr_el0; /* User RW Thread register. */
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@ -2003,7 +2003,10 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
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/* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */
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{ "NSACR", 15,1,1, 0,0,2, 0,0,
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PL3_W | PL1_R, 0, NULL, 0,
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offsetof(CPUARMState, cp15.nsacr), },
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offsetof(CPUARMState, cp15.nsacr) },
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{ "MVBAR", 15,12,0, 0,0,1, 0,0,
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PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mvbar), {0, 0},
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NULL, NULL, vbar_write },
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REGINFO_SENTINEL
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};
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@ -3781,15 +3784,15 @@ void arm_cpu_do_interrupt(CPUState *cs)
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return; /* Never happens. Keep compiler happy. */
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}
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/* High vectors. */
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if (env->cp15.c1_sys & SCTLR_V) {
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/* when enabled, base address cannot be remapped. */
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if (new_mode == ARM_CPU_MODE_MON) {
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addr += env->cp15.mvbar;
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} else if (env->cp15.c1_sys & SCTLR_V) {
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/* High vectors. When enabled, base address cannot be remapped. */
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addr += 0xffff0000;
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} else {
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/* ARM v7 architectures provide a vector base address register to remap
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* the interrupt vector table.
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* This register is only followed in non-monitor mode, and has a secure
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* and un-secure copy. Since the cpu is always in a un-secure operation
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* and is never in monitor mode this feature is always active.
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* This register is only followed in non-monitor mode, and is banked.
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* Note: only bits 31:5 are valid.
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*/
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addr += env->cp15.vbar_el[1];
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