yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-03-24 10:55:04 +00:00
Code Issues Packages Projects Releases Wiki Activity

target-arm: add MVBAR support

Browse source 
Use MVBAR register as exception vector base address for
exceptions taken to CPU monitor mode.

Backports commit e89e51a17ea0d8aef9bf9b766c98f963e835fbf2 from qemu
This commit is contained in:
Fabian Aggeler 2018-02-11 19:07:56 -05:00 committed by Lioncash
parent e49d9d3f30
commit ca0608f68d
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 10 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
qemu/target-arm/cpu.h
View file

@ -213,6 +213,7 @@ typedef struct CPUARMState {
uint32_t c9_pminten; /* perf monitor interrupt enables */ uint32_t c9_pminten; /* perf monitor interrupt enables */
uint64_t mair_el1; uint64_t mair_el1;
uint64_t vbar_el[4]; /* vector base address register */ uint64_t vbar_el[4]; /* vector base address register */
uint32_t mvbar; /* (monitor) vector base address register */
uint32_t c13_fcse; /* FCSE PID. */ uint32_t c13_fcse; /* FCSE PID. */
uint64_t contextidr_el1; /* Context ID. */ uint64_t contextidr_el1; /* Context ID. */
uint64_t tpidr_el0; /* User RW Thread register. */ uint64_t tpidr_el0; /* User RW Thread register. */

15
qemu/target-arm/helper.c
View file

@ -2003,7 +2003,10 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
/* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */ /* TODO: Implement NSACR trapping of secure EL1 accesses to EL3 */
{ "NSACR", 15,1,1, 0,0,2, 0,0, { "NSACR", 15,1,1, 0,0,2, 0,0,
PL3_W | PL1_R, 0, NULL, 0, PL3_W | PL1_R, 0, NULL, 0,
offsetof(CPUARMState, cp15.nsacr), }, offsetof(CPUARMState, cp15.nsacr) },
{ "MVBAR", 15,12,0, 0,0,1, 0,0,
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mvbar), {0, 0},
NULL, NULL, vbar_write },
REGINFO_SENTINEL REGINFO_SENTINEL
}; };
@ -3781,15 +3784,15 @@ void arm_cpu_do_interrupt(CPUState *cs)
return; /* Never happens. Keep compiler happy. */ return; /* Never happens. Keep compiler happy. */
} }
/* High vectors. */ /* High vectors. */
if (env->cp15.c1_sys & SCTLR_V) { if (new_mode == ARM_CPU_MODE_MON) {
/* when enabled, base address cannot be remapped. */ addr += env->cp15.mvbar;
} else if (env->cp15.c1_sys & SCTLR_V) {
/* High vectors. When enabled, base address cannot be remapped. */
addr += 0xffff0000; addr += 0xffff0000;
} else { } else {
/* ARM v7 architectures provide a vector base address register to remap /* ARM v7 architectures provide a vector base address register to remap
* the interrupt vector table. * the interrupt vector table.
* This register is only followed in non-monitor mode, and has a secure * This register is only followed in non-monitor mode, and is banked.
* and un-secure copy. Since the cpu is always in a un-secure operation
* and is never in monitor mode this feature is always active.
* Note: only bits 31:5 are valid. * Note: only bits 31:5 are valid.
*/ */
addr += env->cp15.vbar_el[1]; addr += env->cp15.vbar_el[1];