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target/arm: Decode aa32 armv8.1 three same

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Backports commit 36a719348a9744d17c6ef6bac01bcb5fcd279753 from qemu
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Richard Henderson 2018-03-09 00:18:28 -05:00 committed by Lioncash
parent 152c9484bd
commit ca4ceb2dd7
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 68 additions and 19 deletions
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87
qemu/target/arm/translate.c
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@ -26,6 +26,7 @@
#include "internals.h"
#include "exec/exec-all.h"
#include "tcg-op.h"
#include "tcg-op-gvec.h"
#include "qemu/log.h"
#include "qemu/bitops.h"
#include "arm_ldst.h"
@ -5526,9 +5527,9 @@ static void gen_neon_narrow_op(DisasContext *s, int op, int u, int size,
#define NEON_3R_VPMAX 20
#define NEON_3R_VPMIN 21
#define NEON_3R_VQDMULH_VQRDMULH 22
#define NEON_3R_VPADD 23
#define NEON_3R_VPADD_VQRDMLAH 23
#define NEON_3R_SHA 24 /* SHA1C,SHA1P,SHA1M,SHA1SU0,SHA256H{2},SHA256SU1 */
#define NEON_3R_VFM 25 /* VFMA, VFMS : float fused multiply-add */
#define NEON_3R_VFM_VQRDMLSH 25 /* VFMA, VFMS, VQRDMLSH */
#define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */
#define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */
#define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */
@ -5560,9 +5561,9 @@ static const uint8_t neon_3r_sizes[] = {
/*NEON_3R_VPMAX*/ 0x7,
/*NEON_3R_VPMIN*/ 0x7,
/*NEON_3R_VQDMULH_VQRDMULH*/ 0x6,
/*NEON_3R_VPADD*/ 0x7,
/*NEON_3R_VPADD_VQRDMLAH*/ 0x7,
/*NEON_3R_SHA*/ 0xf, /* size field encodes op type */
/*NEON_3R_VFM*/ 0x5, /* size bit 1 encodes op */
/*NEON_3R_VFM_VQRDMLSH*/ 0x7, /* For VFM, size bit 1 encodes op */
/*NEON_3R_FLOAT_ARITH*/ 0x5, /* size bit 1 encodes op */
/*NEON_3R_FLOAT_MULTIPLY*/ 0x5, /* size bit 1 encodes op */
/*NEON_3R_FLOAT_CMP*/ 0x5, /* size bit 1 encodes op */
@ -5743,6 +5744,23 @@ static const uint8_t neon_2rm_sizes[] = {
/*NEON_2RM_VCVT_UF*/ 0x4,
};
/* Expand v8.1 simd helper. */
static int do_v81_helper(DisasContext *s, gen_helper_gvec_3_ptr *fn,
int q, int rd, int rn, int rm)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
if (arm_dc_feature(s, ARM_FEATURE_V8_RDM)) {
int opr_sz = (1 + q) * 8;
tcg_gen_gvec_3_ptr(tcg_ctx, vfp_reg_offset(1, rd),
vfp_reg_offset(1, rn),
vfp_reg_offset(1, rm), tcg_ctx->cpu_env,
opr_sz, opr_sz, 0, fn);
return 0;
}
return 1;
}
/* Translate a NEON data processing instruction. Return nonzero if the
instruction is invalid.
We process data in a mixture of 32-bit and 64-bit chunks.
@ -5796,12 +5814,13 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
if (q && ((rd | rn | rm) & 1)) {
return 1;
}
/*
* The SHA-1/SHA-256 3-register instructions require special treatment
* here, as their size field is overloaded as an op type selector, and
* they all consume their input in a single pass.
*/
if (op == NEON_3R_SHA) {
switch (op) {
case NEON_3R_SHA:
/* The SHA-1/SHA-256 3-register instructions require special
* treatment here, as their size field is overloaded as an
* op type selector, and they all consume their input in a
* single pass.
*/
if (!q) {
return 1;
}
@ -5838,6 +5857,40 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
tcg_temp_free_ptr(tcg_ctx, ptr2);
tcg_temp_free_ptr(tcg_ctx, ptr3);
return 0;
case NEON_3R_VPADD_VQRDMLAH:
if (!u) {
break; /* VPADD */
}
/* VQRDMLAH */
switch (size) {
case 1:
return do_v81_helper(s, gen_helper_gvec_qrdmlah_s16,
q, rd, rn, rm);
case 2:
return do_v81_helper(s, gen_helper_gvec_qrdmlah_s32,
q, rd, rn, rm);
}
return 1;
case NEON_3R_VFM_VQRDMLSH:
if (!u) {
/* VFM, VFMS */
if (size == 1) {
return 1;
}
break;
}
/* VQRDMLSH */
switch (size) {
case 1:
return do_v81_helper(s, gen_helper_gvec_qrdmlsh_s16,
q, rd, rn, rm);
case 2:
return do_v81_helper(s, gen_helper_gvec_qrdmlsh_s32,
q, rd, rn, rm);
}
return 1;
}
if (size == 3 && op != NEON_3R_LOGIC) {
/* 64-bit element instructions. */
@ -5923,11 +5976,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
rm = rtmp;
}
break;
case NEON_3R_VPADD:
if (u) {
return 1;
}
/* Fall through */
case NEON_3R_VPADD_VQRDMLAH:
case NEON_3R_VPMAX:
case NEON_3R_VPMIN:
pairwise = 1;
@ -5961,8 +6010,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
return 1;
}
break;
case NEON_3R_VFM:
if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || u) {
case NEON_3R_VFM_VQRDMLSH:
if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) {
return 1;
}
break;
@ -6159,7 +6208,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
}
}
break;
case NEON_3R_VPADD:
case NEON_3R_VPADD_VQRDMLAH:
switch (size) {
case 0: gen_helper_neon_padd_u8(tcg_ctx, tmp, tmp, tmp2); break;
case 1: gen_helper_neon_padd_u16(tcg_ctx, tmp, tmp, tmp2); break;
@ -6258,7 +6307,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
}
}
break;
case NEON_3R_VFM:
case NEON_3R_VFM_VQRDMLSH:
{
/* VFMA, VFMS: fused multiply-add */
TCGv_ptr fpstatus = get_fpstatus_ptr(s, 1);