tcg: Add support for vector bitwise select

This operation performs d = (b & a) | (c & ~a), and is present
on a majority of host vector units. Include gvec expanders.

Backports commit 38dc12947ec9106237f9cdbd428792c985cd86ae from qemu

qemu/aarch64.h

@@ -1127,6 +1127,7 @@
 #define helper_gvec_and helper_gvec_and_aarch64
 #define helper_gvec_andc helper_gvec_andc_aarch64
 #define helper_gvec_ands helper_gvec_ands_aarch64
+#define helper_gvec_bitsel helper_gvec_bitsel_aarch64
 #define helper_gvec_dup8 helper_gvec_dup8_aarch64
 #define helper_gvec_dup16 helper_gvec_dup16_aarch64
 #define helper_gvec_dup32 helper_gvec_dup32_aarch64
@@ -2785,6 +2786,7 @@
 #define tcg_gen_atomic_xchg_i64 tcg_gen_atomic_xchg_i64_aarch64
 #define tcg_gen_atomic_xor_fetch_i32 tcg_gen_atomic_xor_fetch_i32_aarch64
 #define tcg_gen_atomic_xor_fetch_i64 tcg_gen_atomic_xor_fetch_i64_aarch64
+#define tcg_gen_bitsel_vec tcg_gen_bitsel_vec_aarch64
 #define tcg_gen_br tcg_gen_br_aarch64
 #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_aarch64
 #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_aarch64
@@ -2880,6 +2882,7 @@
 #define tcg_gen_gvec_andc tcg_gen_gvec_andc_aarch64
 #define tcg_gen_gvec_andi tcg_gen_gvec_andi_aarch64
 #define tcg_gen_gvec_ands tcg_gen_gvec_ands_aarch64
+#define tcg_gen_gvec_bitsel tcg_gen_gvec_bitsel_aarch64
 #define tcg_gen_gvec_cmp tcg_gen_gvec_cmp_aarch64
 #define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_aarch64
 #define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_aarch64

qemu/aarch64eb.h

@@ -1127,6 +1127,7 @@
 #define helper_gvec_and helper_gvec_and_aarch64eb
 #define helper_gvec_andc helper_gvec_andc_aarch64eb
 #define helper_gvec_ands helper_gvec_ands_aarch64eb
+#define helper_gvec_bitsel helper_gvec_bitsel_aarch64eb
 #define helper_gvec_dup8 helper_gvec_dup8_aarch64eb
 #define helper_gvec_dup16 helper_gvec_dup16_aarch64eb
 #define helper_gvec_dup32 helper_gvec_dup32_aarch64eb
@@ -2785,6 +2786,7 @@
 #define tcg_gen_atomic_xchg_i64 tcg_gen_atomic_xchg_i64_aarch64eb
 #define tcg_gen_atomic_xor_fetch_i32 tcg_gen_atomic_xor_fetch_i32_aarch64eb
 #define tcg_gen_atomic_xor_fetch_i64 tcg_gen_atomic_xor_fetch_i64_aarch64eb
+#define tcg_gen_bitsel_vec tcg_gen_bitsel_vec_aarch64eb
 #define tcg_gen_br tcg_gen_br_aarch64eb
 #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_aarch64eb
 #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_aarch64eb
@@ -2880,6 +2882,7 @@
 #define tcg_gen_gvec_andc tcg_gen_gvec_andc_aarch64eb
 #define tcg_gen_gvec_andi tcg_gen_gvec_andi_aarch64eb
 #define tcg_gen_gvec_ands tcg_gen_gvec_ands_aarch64eb
+#define tcg_gen_gvec_bitsel tcg_gen_gvec_bitsel_aarch64eb
 #define tcg_gen_gvec_cmp tcg_gen_gvec_cmp_aarch64eb
 #define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_aarch64eb
 #define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_aarch64eb

qemu/accel/tcg/tcg-runtime-gvec.c

@@ -1444,3 +1444,17 @@ void HELPER(gvec_umax64)(void *d, void *a, void *b, uint32_t desc)
     }
     clear_high(d, oprsz, desc);
 }
+
+void HELPER(gvec_bitsel)(void *d, void *a, void *b, void *c, uint32_t desc)
+{
+    intptr_t oprsz = simd_oprsz(desc);
+    intptr_t i;
+
+    for (i = 0; i < oprsz; i += sizeof(vec64)) {
+        vec64 aa = *(vec64 *)(a + i);
+        vec64 bb = *(vec64 *)(b + i);
+        vec64 cc = *(vec64 *)(c + i);
+        *(vec64 *)(d + i) = (bb & aa) | (cc & ~aa);
+    }
+    clear_high(d, oprsz, desc);
+}

qemu/accel/tcg/tcg-runtime.h

@@ -303,3 +303,5 @@ DEF_HELPER_FLAGS_4(gvec_leu8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(gvec_leu16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(gvec_leu32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(gvec_leu64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_5(gvec_bitsel, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)

qemu/arm.h

@@ -1127,6 +1127,7 @@
 #define helper_gvec_and helper_gvec_and_arm
 #define helper_gvec_andc helper_gvec_andc_arm
 #define helper_gvec_ands helper_gvec_ands_arm
+#define helper_gvec_bitsel helper_gvec_bitsel_arm
 #define helper_gvec_dup8 helper_gvec_dup8_arm
 #define helper_gvec_dup16 helper_gvec_dup16_arm
 #define helper_gvec_dup32 helper_gvec_dup32_arm
@@ -2785,6 +2786,7 @@
 #define tcg_gen_atomic_xchg_i64 tcg_gen_atomic_xchg_i64_arm
 #define tcg_gen_atomic_xor_fetch_i32 tcg_gen_atomic_xor_fetch_i32_arm
 #define tcg_gen_atomic_xor_fetch_i64 tcg_gen_atomic_xor_fetch_i64_arm
+#define tcg_gen_bitsel_vec tcg_gen_bitsel_vec_arm
 #define tcg_gen_br tcg_gen_br_arm
 #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_arm
 #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_arm
@@ -2880,6 +2882,7 @@
 #define tcg_gen_gvec_andc tcg_gen_gvec_andc_arm
 #define tcg_gen_gvec_andi tcg_gen_gvec_andi_arm
 #define tcg_gen_gvec_ands tcg_gen_gvec_ands_arm
+#define tcg_gen_gvec_bitsel tcg_gen_gvec_bitsel_arm
 #define tcg_gen_gvec_cmp tcg_gen_gvec_cmp_arm
 #define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_arm
 #define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_arm

qemu/armeb.h

@@ -1127,6 +1127,7 @@
 #define helper_gvec_and helper_gvec_and_armeb
 #define helper_gvec_andc helper_gvec_andc_armeb
 #define helper_gvec_ands helper_gvec_ands_armeb
+#define helper_gvec_bitsel helper_gvec_bitsel_armeb
 #define helper_gvec_dup8 helper_gvec_dup8_armeb
 #define helper_gvec_dup16 helper_gvec_dup16_armeb
 #define helper_gvec_dup32 helper_gvec_dup32_armeb
@@ -2785,6 +2786,7 @@
 #define tcg_gen_atomic_xchg_i64 tcg_gen_atomic_xchg_i64_armeb
 #define tcg_gen_atomic_xor_fetch_i32 tcg_gen_atomic_xor_fetch_i32_armeb
 #define tcg_gen_atomic_xor_fetch_i64 tcg_gen_atomic_xor_fetch_i64_armeb
+#define tcg_gen_bitsel_vec tcg_gen_bitsel_vec_armeb
 #define tcg_gen_br tcg_gen_br_armeb
 #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_armeb
 #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_armeb
@@ -2880,6 +2882,7 @@
 #define tcg_gen_gvec_andc tcg_gen_gvec_andc_armeb
 #define tcg_gen_gvec_andi tcg_gen_gvec_andi_armeb
 #define tcg_gen_gvec_ands tcg_gen_gvec_ands_armeb
+#define tcg_gen_gvec_bitsel tcg_gen_gvec_bitsel_armeb
 #define tcg_gen_gvec_cmp tcg_gen_gvec_cmp_armeb
 #define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_armeb
 #define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_armeb

qemu/header_gen.py

@@ -1133,6 +1133,7 @@ symbols = (
     'helper_gvec_and',
     'helper_gvec_andc',
     'helper_gvec_ands',
+    'helper_gvec_bitsel',
     'helper_gvec_dup8',
     'helper_gvec_dup16',
     'helper_gvec_dup32',
@@ -2791,6 +2792,7 @@ symbols = (
     'tcg_gen_atomic_xchg_i64',
     'tcg_gen_atomic_xor_fetch_i32',
     'tcg_gen_atomic_xor_fetch_i64',
+    'tcg_gen_bitsel_vec',
     'tcg_gen_br',
     'tcg_gen_brcond_i32',
     'tcg_gen_brcond_i64',
@@ -2886,6 +2888,7 @@ symbols = (
     'tcg_gen_gvec_andc',
     'tcg_gen_gvec_andi',
     'tcg_gen_gvec_ands',
+    'tcg_gen_gvec_bitsel',
     'tcg_gen_gvec_cmp',
     'tcg_gen_gvec_dup8i',
     'tcg_gen_gvec_dup16i',

qemu/m68k.h

@@ -1127,6 +1127,7 @@
 #define helper_gvec_and helper_gvec_and_m68k
 #define helper_gvec_andc helper_gvec_andc_m68k
 #define helper_gvec_ands helper_gvec_ands_m68k
+#define helper_gvec_bitsel helper_gvec_bitsel_m68k
 #define helper_gvec_dup8 helper_gvec_dup8_m68k
 #define helper_gvec_dup16 helper_gvec_dup16_m68k
 #define helper_gvec_dup32 helper_gvec_dup32_m68k
@@ -2785,6 +2786,7 @@
 #define tcg_gen_atomic_xchg_i64 tcg_gen_atomic_xchg_i64_m68k
 #define tcg_gen_atomic_xor_fetch_i32 tcg_gen_atomic_xor_fetch_i32_m68k
 #define tcg_gen_atomic_xor_fetch_i64 tcg_gen_atomic_xor_fetch_i64_m68k
+#define tcg_gen_bitsel_vec tcg_gen_bitsel_vec_m68k
 #define tcg_gen_br tcg_gen_br_m68k
 #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_m68k
 #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_m68k
@@ -2880,6 +2882,7 @@
 #define tcg_gen_gvec_andc tcg_gen_gvec_andc_m68k
 #define tcg_gen_gvec_andi tcg_gen_gvec_andi_m68k
 #define tcg_gen_gvec_ands tcg_gen_gvec_ands_m68k
+#define tcg_gen_gvec_bitsel tcg_gen_gvec_bitsel_m68k
 #define tcg_gen_gvec_cmp tcg_gen_gvec_cmp_m68k
 #define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_m68k
 #define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_m68k

qemu/mips.h

@@ -1127,6 +1127,7 @@
 #define helper_gvec_and helper_gvec_and_mips
 #define helper_gvec_andc helper_gvec_andc_mips
 #define helper_gvec_ands helper_gvec_ands_mips
+#define helper_gvec_bitsel helper_gvec_bitsel_mips
 #define helper_gvec_dup8 helper_gvec_dup8_mips
 #define helper_gvec_dup16 helper_gvec_dup16_mips
 #define helper_gvec_dup32 helper_gvec_dup32_mips
@@ -2785,6 +2786,7 @@
 #define tcg_gen_atomic_xchg_i64 tcg_gen_atomic_xchg_i64_mips
 #define tcg_gen_atomic_xor_fetch_i32 tcg_gen_atomic_xor_fetch_i32_mips
 #define tcg_gen_atomic_xor_fetch_i64 tcg_gen_atomic_xor_fetch_i64_mips
+#define tcg_gen_bitsel_vec tcg_gen_bitsel_vec_mips
 #define tcg_gen_br tcg_gen_br_mips
 #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_mips
 #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_mips
@@ -2880,6 +2882,7 @@
 #define tcg_gen_gvec_andc tcg_gen_gvec_andc_mips
 #define tcg_gen_gvec_andi tcg_gen_gvec_andi_mips
 #define tcg_gen_gvec_ands tcg_gen_gvec_ands_mips
+#define tcg_gen_gvec_bitsel tcg_gen_gvec_bitsel_mips
 #define tcg_gen_gvec_cmp tcg_gen_gvec_cmp_mips
 #define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_mips
 #define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_mips

qemu/mips64.h

@@ -1127,6 +1127,7 @@
 #define helper_gvec_and helper_gvec_and_mips64
 #define helper_gvec_andc helper_gvec_andc_mips64
 #define helper_gvec_ands helper_gvec_ands_mips64
+#define helper_gvec_bitsel helper_gvec_bitsel_mips64
 #define helper_gvec_dup8 helper_gvec_dup8_mips64
 #define helper_gvec_dup16 helper_gvec_dup16_mips64
 #define helper_gvec_dup32 helper_gvec_dup32_mips64
@@ -2785,6 +2786,7 @@
 #define tcg_gen_atomic_xchg_i64 tcg_gen_atomic_xchg_i64_mips64
 #define tcg_gen_atomic_xor_fetch_i32 tcg_gen_atomic_xor_fetch_i32_mips64
 #define tcg_gen_atomic_xor_fetch_i64 tcg_gen_atomic_xor_fetch_i64_mips64
+#define tcg_gen_bitsel_vec tcg_gen_bitsel_vec_mips64
 #define tcg_gen_br tcg_gen_br_mips64
 #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_mips64
 #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_mips64
@@ -2880,6 +2882,7 @@
 #define tcg_gen_gvec_andc tcg_gen_gvec_andc_mips64
 #define tcg_gen_gvec_andi tcg_gen_gvec_andi_mips64
 #define tcg_gen_gvec_ands tcg_gen_gvec_ands_mips64
+#define tcg_gen_gvec_bitsel tcg_gen_gvec_bitsel_mips64
 #define tcg_gen_gvec_cmp tcg_gen_gvec_cmp_mips64
 #define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_mips64
 #define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_mips64

qemu/mips64el.h

@@ -1127,6 +1127,7 @@
 #define helper_gvec_and helper_gvec_and_mips64el
 #define helper_gvec_andc helper_gvec_andc_mips64el
 #define helper_gvec_ands helper_gvec_ands_mips64el
+#define helper_gvec_bitsel helper_gvec_bitsel_mips64el
 #define helper_gvec_dup8 helper_gvec_dup8_mips64el
 #define helper_gvec_dup16 helper_gvec_dup16_mips64el
 #define helper_gvec_dup32 helper_gvec_dup32_mips64el
@@ -2785,6 +2786,7 @@
 #define tcg_gen_atomic_xchg_i64 tcg_gen_atomic_xchg_i64_mips64el
 #define tcg_gen_atomic_xor_fetch_i32 tcg_gen_atomic_xor_fetch_i32_mips64el
 #define tcg_gen_atomic_xor_fetch_i64 tcg_gen_atomic_xor_fetch_i64_mips64el
+#define tcg_gen_bitsel_vec tcg_gen_bitsel_vec_mips64el
 #define tcg_gen_br tcg_gen_br_mips64el
 #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_mips64el
 #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_mips64el
@@ -2880,6 +2882,7 @@
 #define tcg_gen_gvec_andc tcg_gen_gvec_andc_mips64el
 #define tcg_gen_gvec_andi tcg_gen_gvec_andi_mips64el
 #define tcg_gen_gvec_ands tcg_gen_gvec_ands_mips64el
+#define tcg_gen_gvec_bitsel tcg_gen_gvec_bitsel_mips64el
 #define tcg_gen_gvec_cmp tcg_gen_gvec_cmp_mips64el
 #define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_mips64el
 #define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_mips64el

qemu/mipsel.h

@@ -1127,6 +1127,7 @@
 #define helper_gvec_and helper_gvec_and_mipsel
 #define helper_gvec_andc helper_gvec_andc_mipsel
 #define helper_gvec_ands helper_gvec_ands_mipsel
+#define helper_gvec_bitsel helper_gvec_bitsel_mipsel
 #define helper_gvec_dup8 helper_gvec_dup8_mipsel
 #define helper_gvec_dup16 helper_gvec_dup16_mipsel
 #define helper_gvec_dup32 helper_gvec_dup32_mipsel
@@ -2785,6 +2786,7 @@
 #define tcg_gen_atomic_xchg_i64 tcg_gen_atomic_xchg_i64_mipsel
 #define tcg_gen_atomic_xor_fetch_i32 tcg_gen_atomic_xor_fetch_i32_mipsel
 #define tcg_gen_atomic_xor_fetch_i64 tcg_gen_atomic_xor_fetch_i64_mipsel
+#define tcg_gen_bitsel_vec tcg_gen_bitsel_vec_mipsel
 #define tcg_gen_br tcg_gen_br_mipsel
 #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_mipsel
 #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_mipsel
@@ -2880,6 +2882,7 @@
 #define tcg_gen_gvec_andc tcg_gen_gvec_andc_mipsel
 #define tcg_gen_gvec_andi tcg_gen_gvec_andi_mipsel
 #define tcg_gen_gvec_ands tcg_gen_gvec_ands_mipsel
+#define tcg_gen_gvec_bitsel tcg_gen_gvec_bitsel_mipsel
 #define tcg_gen_gvec_cmp tcg_gen_gvec_cmp_mipsel
 #define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_mipsel
 #define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_mipsel

qemu/powerpc.h

@@ -1127,6 +1127,7 @@
 #define helper_gvec_and helper_gvec_and_powerpc
 #define helper_gvec_andc helper_gvec_andc_powerpc
 #define helper_gvec_ands helper_gvec_ands_powerpc
+#define helper_gvec_bitsel helper_gvec_bitsel_powerpc
 #define helper_gvec_dup8 helper_gvec_dup8_powerpc
 #define helper_gvec_dup16 helper_gvec_dup16_powerpc
 #define helper_gvec_dup32 helper_gvec_dup32_powerpc
@@ -2785,6 +2786,7 @@
 #define tcg_gen_atomic_xchg_i64 tcg_gen_atomic_xchg_i64_powerpc
 #define tcg_gen_atomic_xor_fetch_i32 tcg_gen_atomic_xor_fetch_i32_powerpc
 #define tcg_gen_atomic_xor_fetch_i64 tcg_gen_atomic_xor_fetch_i64_powerpc
+#define tcg_gen_bitsel_vec tcg_gen_bitsel_vec_powerpc
 #define tcg_gen_br tcg_gen_br_powerpc
 #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_powerpc
 #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_powerpc
@@ -2880,6 +2882,7 @@
 #define tcg_gen_gvec_andc tcg_gen_gvec_andc_powerpc
 #define tcg_gen_gvec_andi tcg_gen_gvec_andi_powerpc
 #define tcg_gen_gvec_ands tcg_gen_gvec_ands_powerpc
+#define tcg_gen_gvec_bitsel tcg_gen_gvec_bitsel_powerpc
 #define tcg_gen_gvec_cmp tcg_gen_gvec_cmp_powerpc
 #define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_powerpc
 #define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_powerpc

qemu/riscv32.h

@@ -1127,6 +1127,7 @@
 #define helper_gvec_and helper_gvec_and_riscv32
 #define helper_gvec_andc helper_gvec_andc_riscv32
 #define helper_gvec_ands helper_gvec_ands_riscv32
+#define helper_gvec_bitsel helper_gvec_bitsel_riscv32
 #define helper_gvec_dup8 helper_gvec_dup8_riscv32
 #define helper_gvec_dup16 helper_gvec_dup16_riscv32
 #define helper_gvec_dup32 helper_gvec_dup32_riscv32
@@ -2785,6 +2786,7 @@
 #define tcg_gen_atomic_xchg_i64 tcg_gen_atomic_xchg_i64_riscv32
 #define tcg_gen_atomic_xor_fetch_i32 tcg_gen_atomic_xor_fetch_i32_riscv32
 #define tcg_gen_atomic_xor_fetch_i64 tcg_gen_atomic_xor_fetch_i64_riscv32
+#define tcg_gen_bitsel_vec tcg_gen_bitsel_vec_riscv32
 #define tcg_gen_br tcg_gen_br_riscv32
 #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_riscv32
 #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_riscv32
@@ -2880,6 +2882,7 @@
 #define tcg_gen_gvec_andc tcg_gen_gvec_andc_riscv32
 #define tcg_gen_gvec_andi tcg_gen_gvec_andi_riscv32
 #define tcg_gen_gvec_ands tcg_gen_gvec_ands_riscv32
+#define tcg_gen_gvec_bitsel tcg_gen_gvec_bitsel_riscv32
 #define tcg_gen_gvec_cmp tcg_gen_gvec_cmp_riscv32
 #define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_riscv32
 #define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_riscv32

qemu/riscv64.h

@@ -1127,6 +1127,7 @@
 #define helper_gvec_and helper_gvec_and_riscv64
 #define helper_gvec_andc helper_gvec_andc_riscv64
 #define helper_gvec_ands helper_gvec_ands_riscv64
+#define helper_gvec_bitsel helper_gvec_bitsel_riscv64
 #define helper_gvec_dup8 helper_gvec_dup8_riscv64
 #define helper_gvec_dup16 helper_gvec_dup16_riscv64
 #define helper_gvec_dup32 helper_gvec_dup32_riscv64
@@ -2785,6 +2786,7 @@
 #define tcg_gen_atomic_xchg_i64 tcg_gen_atomic_xchg_i64_riscv64
 #define tcg_gen_atomic_xor_fetch_i32 tcg_gen_atomic_xor_fetch_i32_riscv64
 #define tcg_gen_atomic_xor_fetch_i64 tcg_gen_atomic_xor_fetch_i64_riscv64
+#define tcg_gen_bitsel_vec tcg_gen_bitsel_vec_riscv64
 #define tcg_gen_br tcg_gen_br_riscv64
 #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_riscv64
 #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_riscv64
@@ -2880,6 +2882,7 @@
 #define tcg_gen_gvec_andc tcg_gen_gvec_andc_riscv64
 #define tcg_gen_gvec_andi tcg_gen_gvec_andi_riscv64
 #define tcg_gen_gvec_ands tcg_gen_gvec_ands_riscv64
+#define tcg_gen_gvec_bitsel tcg_gen_gvec_bitsel_riscv64
 #define tcg_gen_gvec_cmp tcg_gen_gvec_cmp_riscv64
 #define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_riscv64
 #define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_riscv64

qemu/sparc.h

@@ -1127,6 +1127,7 @@
 #define helper_gvec_and helper_gvec_and_sparc
 #define helper_gvec_andc helper_gvec_andc_sparc
 #define helper_gvec_ands helper_gvec_ands_sparc
+#define helper_gvec_bitsel helper_gvec_bitsel_sparc
 #define helper_gvec_dup8 helper_gvec_dup8_sparc
 #define helper_gvec_dup16 helper_gvec_dup16_sparc
 #define helper_gvec_dup32 helper_gvec_dup32_sparc
@@ -2785,6 +2786,7 @@
 #define tcg_gen_atomic_xchg_i64 tcg_gen_atomic_xchg_i64_sparc
 #define tcg_gen_atomic_xor_fetch_i32 tcg_gen_atomic_xor_fetch_i32_sparc
 #define tcg_gen_atomic_xor_fetch_i64 tcg_gen_atomic_xor_fetch_i64_sparc
+#define tcg_gen_bitsel_vec tcg_gen_bitsel_vec_sparc
 #define tcg_gen_br tcg_gen_br_sparc
 #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_sparc
 #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_sparc
@@ -2880,6 +2882,7 @@
 #define tcg_gen_gvec_andc tcg_gen_gvec_andc_sparc
 #define tcg_gen_gvec_andi tcg_gen_gvec_andi_sparc
 #define tcg_gen_gvec_ands tcg_gen_gvec_ands_sparc
+#define tcg_gen_gvec_bitsel tcg_gen_gvec_bitsel_sparc
 #define tcg_gen_gvec_cmp tcg_gen_gvec_cmp_sparc
 #define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_sparc
 #define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_sparc

qemu/sparc64.h

@@ -1127,6 +1127,7 @@
 #define helper_gvec_and helper_gvec_and_sparc64
 #define helper_gvec_andc helper_gvec_andc_sparc64
 #define helper_gvec_ands helper_gvec_ands_sparc64
+#define helper_gvec_bitsel helper_gvec_bitsel_sparc64
 #define helper_gvec_dup8 helper_gvec_dup8_sparc64
 #define helper_gvec_dup16 helper_gvec_dup16_sparc64
 #define helper_gvec_dup32 helper_gvec_dup32_sparc64
@@ -2785,6 +2786,7 @@
 #define tcg_gen_atomic_xchg_i64 tcg_gen_atomic_xchg_i64_sparc64
 #define tcg_gen_atomic_xor_fetch_i32 tcg_gen_atomic_xor_fetch_i32_sparc64
 #define tcg_gen_atomic_xor_fetch_i64 tcg_gen_atomic_xor_fetch_i64_sparc64
+#define tcg_gen_bitsel_vec tcg_gen_bitsel_vec_sparc64
 #define tcg_gen_br tcg_gen_br_sparc64
 #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_sparc64
 #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_sparc64
@@ -2880,6 +2882,7 @@
 #define tcg_gen_gvec_andc tcg_gen_gvec_andc_sparc64
 #define tcg_gen_gvec_andi tcg_gen_gvec_andi_sparc64
 #define tcg_gen_gvec_ands tcg_gen_gvec_ands_sparc64
+#define tcg_gen_gvec_bitsel tcg_gen_gvec_bitsel_sparc64
 #define tcg_gen_gvec_cmp tcg_gen_gvec_cmp_sparc64
 #define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_sparc64
 #define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_sparc64

qemu/tcg/README

@@ -622,6 +622,10 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
 
   Compare vectors by element, storing -1 for true and 0 for false.
 
+* bitsel_vec v0, v1, v2, v3
+
+  Bitwise select, v0 = (v2 & v1) | (v3 & ~v1), across the entire vector.
+
 *********
 
 Note 1: Some shortcuts are defined when the last operand is known to be

qemu/tcg/aarch64/tcg-target.h

@@ -140,6 +140,7 @@ typedef enum {
 #define TCG_TARGET_HAS_mul_vec          1
 #define TCG_TARGET_HAS_sat_vec          1
 #define TCG_TARGET_HAS_minmax_vec       1
+#define TCG_TARGET_HAS_bitsel_vec       0
 
 #define TCG_TARGET_DEFAULT_MO (0)
 #define TCG_TARGET_HAS_MEMORY_BSWAP     1

qemu/tcg/i386/tcg-target.h

@@ -223,6 +223,7 @@ extern bool have_avx2;
 #define TCG_TARGET_HAS_mul_vec          1
 #define TCG_TARGET_HAS_sat_vec          1
 #define TCG_TARGET_HAS_minmax_vec       1
+#define TCG_TARGET_HAS_bitsel_vec       0
 
 #define TCG_TARGET_deposit_i32_valid(ofs, len) \
     (((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \

qemu/tcg/tcg-op-gvec.c

@@ -3195,3 +3195,26 @@ void tcg_gen_gvec_cmp(TCGContext *s, TCGCond cond, unsigned vece, uint32_t dofs,
         expand_clr(s, dofs + oprsz, maxsz - oprsz);
     }
 }
+
+static void tcg_gen_bitsel_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 c)
+{
+    TCGv_i64 t = tcg_temp_new_i64(s);
+
+    tcg_gen_and_i64(s, t, b, a);
+    tcg_gen_andc_i64(s, d, c, a);
+    tcg_gen_or_i64(s, d, d, t);
+    tcg_temp_free_i64(s, t);
+}
+
+void tcg_gen_gvec_bitsel(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
+                         uint32_t bofs, uint32_t cofs,
+                         uint32_t oprsz, uint32_t maxsz)
+{
+    static const GVecGen4 g = {
+        .fni8 = tcg_gen_bitsel_i64,
+        .fniv = tcg_gen_bitsel_vec,
+        .fno = gen_helper_gvec_bitsel,
+    };
+
+    tcg_gen_gvec_4(s, dofs, aofs, bofs, cofs, oprsz, maxsz, &g);
+}

qemu/tcg/tcg-op-gvec.h

@@ -342,6 +342,13 @@ void tcg_gen_gvec_cmp(TCGContext *s, TCGCond cond, unsigned vece, uint32_t dofs,
                       uint32_t aofs, uint32_t bofs,
                       uint32_t oprsz, uint32_t maxsz);
 
+/*
+ * Perform vector bit select: d = (b & a) | (c & ~a).
+ */
+void tcg_gen_gvec_bitsel(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
+                         uint32_t bofs, uint32_t cofs,
+                         uint32_t oprsz, uint32_t maxsz);
+
 /*
  * 64-bit vector operations.  Use these when the register has been allocated
  * with tcg_global_mem_new_i64, and so we cannot also address it via pointer.

qemu/tcg/tcg-op-vec.c

@@ -89,6 +89,7 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list,
         case INDEX_op_dup2_vec:
         case INDEX_op_ld_vec:
         case INDEX_op_st_vec:
+        case INDEX_op_bitsel_vec:
             /* These opcodes are mandatory and should not be listed.  */
             g_assert_not_reached();
         default:
@@ -692,3 +693,28 @@ void tcg_gen_sars_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv
 {
     do_shifts(s, vece, r, a, b, INDEX_op_sars_vec, INDEX_op_sarv_vec);
 }
+
+void tcg_gen_bitsel_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a,
+                        TCGv_vec b, TCGv_vec c)
+{
+    TCGTemp *rt = tcgv_vec_temp(s, r);
+    TCGTemp *at = tcgv_vec_temp(s, a);
+    TCGTemp *bt = tcgv_vec_temp(s, b);
+    TCGTemp *ct = tcgv_vec_temp(s, c);
+    TCGType type = rt->base_type;
+
+    tcg_debug_assert(at->base_type >= type);
+    tcg_debug_assert(bt->base_type >= type);
+    tcg_debug_assert(ct->base_type >= type);
+
+    if (TCG_TARGET_HAS_bitsel_vec) {
+        vec_gen_4(s, INDEX_op_bitsel_vec, type, MO_8,
+                  temp_arg(rt), temp_arg(at), temp_arg(bt), temp_arg(ct));
+    } else {
+        TCGv_vec t = tcg_temp_new_vec(s, type);
+        tcg_gen_and_vec(s, MO_8, t, a, b);
+        tcg_gen_andc_vec(s, MO_8, r, c, a);
+        tcg_gen_or_vec(s, MO_8, r, r, t);
+        tcg_temp_free_vec(s, t);
+    }
+}

qemu/tcg/tcg-op.h

@@ -1013,6 +1013,9 @@ void tcg_gen_sarv_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_
 void tcg_gen_cmp_vec(TCGContext *, TCGCond cond, unsigned vece, TCGv_vec r,
                      TCGv_vec a, TCGv_vec b);
 
+void tcg_gen_bitsel_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a,
+                        TCGv_vec b, TCGv_vec c);
+
 void tcg_gen_ld_vec(TCGContext *, TCGv_vec r, TCGv_ptr base, TCGArg offset);
 void tcg_gen_st_vec(TCGContext *, TCGv_vec r, TCGv_ptr base, TCGArg offset);
 void tcg_gen_stl_vec(TCGContext *, TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);

qemu/tcg/tcg-opc.h

@@ -261,6 +261,8 @@ DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
 
 DEF(cmp_vec, 1, 2, 1, IMPLVEC)
 
+DEF(bitsel_vec, 1, 3, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_bitsel_vec))
+
 DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
 
 #if TCG_TARGET_MAYBE_vec

qemu/tcg/tcg.c

@@ -1088,6 +1088,8 @@ bool tcg_op_supported(TCGOpcode op)
     case INDEX_op_smax_vec:
     case INDEX_op_umax_vec:
         return have_vec && TCG_TARGET_HAS_minmax_vec;
+    case INDEX_op_bitsel_vec:
+        return have_vec && TCG_TARGET_HAS_bitsel_vec;
 
     default:
         tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS);

qemu/tcg/tcg.h

@@ -190,6 +190,7 @@ typedef uint64_t TCGRegSet;
 #define TCG_TARGET_HAS_mul_vec          0
 #define TCG_TARGET_HAS_sat_vec          0
 #define TCG_TARGET_HAS_minmax_vec       0
+#define TCG_TARGET_HAS_bitsel_vec       0
 #else
 #define TCG_TARGET_MAYBE_vec            1
 #endif
@@ -1176,7 +1177,7 @@ static inline TCGv_ptr tcg_temp_local_new_ptr(TCGContext *s)
 }
 
 // UNICORN: Added
-#define TCG_OP_DEFS_TABLE_SIZE 183
+#define TCG_OP_DEFS_TABLE_SIZE 184
 extern const TCGOpDef tcg_op_defs_org[TCG_OP_DEFS_TABLE_SIZE];
 
 typedef struct TCGTargetOpDef {

qemu/x86_64.h

@@ -1127,6 +1127,7 @@
 #define helper_gvec_and helper_gvec_and_x86_64
 #define helper_gvec_andc helper_gvec_andc_x86_64
 #define helper_gvec_ands helper_gvec_ands_x86_64
+#define helper_gvec_bitsel helper_gvec_bitsel_x86_64
 #define helper_gvec_dup8 helper_gvec_dup8_x86_64
 #define helper_gvec_dup16 helper_gvec_dup16_x86_64
 #define helper_gvec_dup32 helper_gvec_dup32_x86_64
@@ -2785,6 +2786,7 @@
 #define tcg_gen_atomic_xchg_i64 tcg_gen_atomic_xchg_i64_x86_64
 #define tcg_gen_atomic_xor_fetch_i32 tcg_gen_atomic_xor_fetch_i32_x86_64
 #define tcg_gen_atomic_xor_fetch_i64 tcg_gen_atomic_xor_fetch_i64_x86_64
+#define tcg_gen_bitsel_vec tcg_gen_bitsel_vec_x86_64
 #define tcg_gen_br tcg_gen_br_x86_64
 #define tcg_gen_brcond_i32 tcg_gen_brcond_i32_x86_64
 #define tcg_gen_brcond_i64 tcg_gen_brcond_i64_x86_64
@@ -2880,6 +2882,7 @@
 #define tcg_gen_gvec_andc tcg_gen_gvec_andc_x86_64
 #define tcg_gen_gvec_andi tcg_gen_gvec_andi_x86_64
 #define tcg_gen_gvec_ands tcg_gen_gvec_ands_x86_64
+#define tcg_gen_gvec_bitsel tcg_gen_gvec_bitsel_x86_64
 #define tcg_gen_gvec_cmp tcg_gen_gvec_cmp_x86_64
 #define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_x86_64
 #define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_x86_64