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target/mips: Add emulation of MXU instruction S8LDD

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Backports commit be57bcdb2ed8a4b41be05c8dc42bdec5174f43d6 from qemu
This commit is contained in:
Craig Janeczek 2018-11-11 06:15:50 -05:00 committed by Lioncash
parent 914c0cea7c
commit cad0283888
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 88 additions and 3 deletions
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91
qemu/target/mips/translate.c
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@ -24238,6 +24238,93 @@ static void gen_mxu_s32m2i(DisasContext *ctx)
tcg_temp_free(tcg_ctx, t0); tcg_temp_free(tcg_ctx, t0);
} }
/*
* S8LDD XRa, Rb, s8, optn3 - Load a byte from memory to XRF
*/
static void gen_mxu_s8ldd(DisasContext *ctx)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0, t1;
TCGLabel *l0;
uint32_t XRa, Rb, s8, optn3;
t0 = tcg_temp_new(tcg_ctx);
t1 = tcg_temp_new(tcg_ctx);
l0 = gen_new_label(tcg_ctx);
XRa = extract32(ctx->opcode, 6, 4);
s8 = extract32(ctx->opcode, 10, 8);
optn3 = extract32(ctx->opcode, 18, 3);
Rb = extract32(ctx->opcode, 21, 5);
gen_load_mxu_cr(ctx, t0);
tcg_gen_andi_tl(tcg_ctx, t0, t0, MXU_CR_MXU_EN);
tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_NE, t0, MXU_CR_MXU_EN, l0);
gen_load_gpr(ctx, t0, Rb);
tcg_gen_addi_tl(tcg_ctx, t0, t0, (int8_t)s8);
switch (optn3) {
/* XRa[7:0] = tmp8 */
case MXU_OPTN3_PTN0:
tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, ctx->mem_idx, MO_UB);
gen_load_mxu_gpr(ctx, t0, XRa);
tcg_gen_deposit_tl(tcg_ctx, t0, t0, t1, 0, 8);
break;
/* XRa[15:8] = tmp8 */
case MXU_OPTN3_PTN1:
tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, ctx->mem_idx, MO_UB);
gen_load_mxu_gpr(ctx, t0, XRa);
tcg_gen_deposit_tl(tcg_ctx, t0, t0, t1, 8, 8);
break;
/* XRa[23:16] = tmp8 */
case MXU_OPTN3_PTN2:
tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, ctx->mem_idx, MO_UB);
gen_load_mxu_gpr(ctx, t0, XRa);
tcg_gen_deposit_tl(tcg_ctx, t0, t0, t1, 16, 8);
break;
/* XRa[31:24] = tmp8 */
case MXU_OPTN3_PTN3:
tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, ctx->mem_idx, MO_UB);
gen_load_mxu_gpr(ctx, t0, XRa);
tcg_gen_deposit_tl(tcg_ctx, t0, t0, t1, 24, 8);
break;
/* XRa = {8'b0, tmp8, 8'b0, tmp8} */
case MXU_OPTN3_PTN4:
tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, ctx->mem_idx, MO_UB);
tcg_gen_deposit_tl(tcg_ctx, t0, t1, t1, 16, 16);
break;
/* XRa = {tmp8, 8'b0, tmp8, 8'b0} */
case MXU_OPTN3_PTN5:
tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, ctx->mem_idx, MO_UB);
tcg_gen_shli_tl(tcg_ctx, t1, t1, 8);
tcg_gen_deposit_tl(tcg_ctx, t0, t1, t1, 16, 16);
break;
/* XRa = {{8{sign of tmp8}}, tmp8, {8{sign of tmp8}}, tmp8} */
case MXU_OPTN3_PTN6:
tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, ctx->mem_idx, MO_SB);
tcg_gen_mov_tl(tcg_ctx, t0, t1);
tcg_gen_andi_tl(tcg_ctx, t0, t0, 0xFF00FFFF);
tcg_gen_shli_tl(tcg_ctx, t1, t1, 16);
tcg_gen_or_tl(tcg_ctx, t0, t0, t1);
break;
/* XRa = {tmp8, tmp8, tmp8, tmp8} */
case MXU_OPTN3_PTN7:
tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, ctx->mem_idx, MO_UB);
tcg_gen_deposit_tl(tcg_ctx, t1, t1, t1, 8, 8);
tcg_gen_deposit_tl(tcg_ctx, t0, t1, t1, 16, 16);
break;
}
gen_store_mxu_gpr(ctx, t0, XRa);
gen_set_label(tcg_ctx, l0);
tcg_temp_free(tcg_ctx, t0);
tcg_temp_free(tcg_ctx, t1);
}
/* /*
* Decoding engine for MXU * Decoding engine for MXU
@ -25283,9 +25370,7 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
generate_exception_end(ctx, EXCP_RI); generate_exception_end(ctx, EXCP_RI);
break; break;
case OPC_MXU_S8LDD: case OPC_MXU_S8LDD:
/* TODO: Implement emulation of S8LDD instruction. */ gen_mxu_s8ldd(ctx);
MIPS_INVAL("OPC_MXU_S8LDD");
generate_exception_end(ctx, EXCP_RI);
break; break;
case OPC_MXU_S8STD: case OPC_MXU_S8STD:
/* TODO: Implement emulation of S8STD instruction. */ /* TODO: Implement emulation of S8STD instruction. */