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target/arm: Add sve-max-vq cpu property to -cpu max

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This allows the default (and maximum) vector length to be set
from the command-line. Which is extraordinarily helpful in
debugging problems depending on vector length without having to
bake knowledge of PR_SET_SVE_VL into every guest binary.

Backports relevant parts of commit
adf92eab90e3f5f34c285da6d14d48952b7a8e72 from qemu
This commit is contained in:
Richard Henderson 2018-08-17 13:57:49 -04:00 committed by Lioncash
parent 1d3cf8a0b0
commit cb11b3a6bd
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GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 8 additions and 3 deletions
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6
qemu/target/arm/cpu.c
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@ -160,9 +160,9 @@ static void arm_cpu_reset(CPUState *s)
env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
env->cp15.cptr_el[3] |= CPTR_EZ; env->cp15.cptr_el[3] |= CPTR_EZ;
/* with maximum vector length */ /* with maximum vector length */
env->vfp.zcr_el[1] = ARM_MAX_VQ - 1; env->vfp.zcr_el[1] = cpu->sve_max_vq - 1;
env->vfp.zcr_el[2] = ARM_MAX_VQ - 1; env->vfp.zcr_el[2] = env->vfp.zcr_el[1];
env->vfp.zcr_el[3] = ARM_MAX_VQ - 1; env->vfp.zcr_el[3] = env->vfp.zcr_el[1];
#else #else
/* Reset into the highest available EL */ /* Reset into the highest available EL */
if (arm_feature(env, ARM_FEATURE_EL3)) { if (arm_feature(env, ARM_FEATURE_EL3)) {

3
qemu/target/arm/cpu.h
View file

@ -827,6 +827,9 @@ typedef struct ARMCPU {
QLIST_HEAD(, ARMELChangeHook) el_change_hooks; QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
int32_t node_id; /* NUMA node this CPU belongs to */ int32_t node_id; /* NUMA node this CPU belongs to */
/* Used to set the maximum vector length the cpu will support. */
uint32_t sve_max_vq;
} ARMCPU; } ARMCPU;
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)

2
qemu/target/arm/cpu64.c
View file

@ -225,6 +225,8 @@ static void aarch64_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
*/ */
cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
cpu->dcz_blocksize = 7; /* 512 bytes */ cpu->dcz_blocksize = 7; /* 512 bytes */
cpu->sve_max_vq = ARM_MAX_VQ;
} }
typedef struct ARMCPUInfo { typedef struct ARMCPUInfo {