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target/arm: Implement SVE Compute Vector Address Group

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Backports commit 4b242d9c1b6beaf5c81d84e956243b614a4a1d84 from qemu
This commit is contained in:
Richard Henderson 2018-05-20 04:56:55 -04:00 committed by Lioncash
parent 45e009269e
commit cb55a3acdb
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GPG key ID: 4E3C3CC1031BA9C7
7 changed files with 106 additions and 0 deletions
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4
qemu/aarch64.h
View file

@ -3282,6 +3282,10 @@
#define helper_sve_add_zpzz_d helper_sve_add_zpzz_d_aarch64
#define helper_sve_add_zpzz_h helper_sve_add_zpzz_h_aarch64
#define helper_sve_add_zpzz_s helper_sve_add_zpzz_s_aarch64
#define helper_sve_adr_p32 helper_sve_adr_p32_aarch64
#define helper_sve_adr_p64 helper_sve_adr_p64_aarch64
#define helper_sve_adr_s32 helper_sve_adr_s32_aarch64
#define helper_sve_adr_u32 helper_sve_adr_u32_aarch64
#define helper_sve_and_pppp helper_sve_and_pppp_aarch64
#define helper_sve_and_zpzz_b helper_sve_and_zpzz_b_aarch64
#define helper_sve_and_zpzz_d helper_sve_and_zpzz_d_aarch64

4
qemu/aarch64eb.h
View file

@ -3282,6 +3282,10 @@
#define helper_sve_add_zpzz_d helper_sve_add_zpzz_d_aarch64eb
#define helper_sve_add_zpzz_h helper_sve_add_zpzz_h_aarch64eb
#define helper_sve_add_zpzz_s helper_sve_add_zpzz_s_aarch64eb
#define helper_sve_adr_p32 helper_sve_adr_p32_aarch64eb
#define helper_sve_adr_p64 helper_sve_adr_p64_aarch64eb
#define helper_sve_adr_s32 helper_sve_adr_s32_aarch64eb
#define helper_sve_adr_u32 helper_sve_adr_u32_aarch64eb
#define helper_sve_and_pppp helper_sve_and_pppp_aarch64eb
#define helper_sve_and_zpzz_b helper_sve_and_zpzz_b_aarch64eb
#define helper_sve_and_zpzz_d helper_sve_and_zpzz_d_aarch64eb

4
qemu/header_gen.py
View file

@ -3303,6 +3303,10 @@ aarch64_symbols = (
'helper_sve_add_zpzz_d',
'helper_sve_add_zpzz_h',
'helper_sve_add_zpzz_s',
'helper_sve_adr_p32',
'helper_sve_adr_p64',
'helper_sve_adr_s32',
'helper_sve_adr_u32',
'helper_sve_and_pppp',
'helper_sve_and_zpzz_b',
'helper_sve_and_zpzz_d',

5
qemu/target/arm/helper-sve.h
View file

@ -380,6 +380,11 @@ DEF_HELPER_FLAGS_4(sve_lsl_zzw_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_lsl_zzw_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_lsl_zzw_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_adr_p32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_adr_p64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_adr_s32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sve_adr_u32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)

12
qemu/target/arm/sve.decode
View file

@ -48,6 +48,7 @@
&rr_esz rd rn esz
&rri rd rn imm
&rrri rd rn rm imm
&rri_esz rd rn imm esz
&rrr_esz rd rn rm esz
&rpr_esz rd pg rn esz
@ -75,6 +76,9 @@
# Three operand, vector element size
@rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz
# Three operand with "memory" size, aka immediate left shift
@rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri
# Two register operand, with governing predicate, vector element size
@rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \
&rprr_esz rn=%reg_movprfx
@ -276,6 +280,14 @@ ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm
LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm
LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm
### SVE Compute Vector Address Group
# SVE vector address generation
ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
### SVE Predicate Logical Operations Group
# SVE predicate logical operations

40
qemu/target/arm/sve_helper.c
View file

@ -1061,3 +1061,43 @@ void HELPER(sve_index_d)(void *vd, uint64_t start,
d[i] = start + i * incr;
}
}
void HELPER(sve_adr_p32)(void *vd, void *vn, void *vm, uint32_t desc)
{
intptr_t i, opr_sz = simd_oprsz(desc) / 4;
uint32_t sh = simd_data(desc);
uint32_t *d = vd, *n = vn, *m = vm;
for (i = 0; i < opr_sz; i += 1) {
d[i] = n[i] + (m[i] << sh);
}
}
void HELPER(sve_adr_p64)(void *vd, void *vn, void *vm, uint32_t desc)
{
intptr_t i, opr_sz = simd_oprsz(desc) / 8;
uint64_t sh = simd_data(desc);
uint64_t *d = vd, *n = vn, *m = vm;
for (i = 0; i < opr_sz; i += 1) {
d[i] = n[i] + (m[i] << sh);
}
}
void HELPER(sve_adr_s32)(void *vd, void *vn, void *vm, uint32_t desc)
{
intptr_t i, opr_sz = simd_oprsz(desc) / 8;
uint64_t sh = simd_data(desc);
uint64_t *d = vd, *n = vn, *m = vm;
for (i = 0; i < opr_sz; i += 1) {
d[i] = n[i] + ((uint64_t)(int32_t)m[i] << sh);
}
}
void HELPER(sve_adr_u32)(void *vd, void *vn, void *vm, uint32_t desc)
{
intptr_t i, opr_sz = simd_oprsz(desc) / 8;
uint64_t sh = simd_data(desc);
uint64_t *d = vd, *n = vn, *m = vm;
for (i = 0; i < opr_sz; i += 1) {
d[i] = n[i] + ((uint64_t)(uint32_t)m[i] << sh);
}
}

37
qemu/target/arm/translate-sve.c
View file

@ -914,6 +914,43 @@ static bool trans_RDVL(DisasContext *s, arg_RDVL *a, uint32_t insn)
return true;
}
/*
*** SVE Compute Vector Address Group
*/
static bool do_adr(DisasContext *s, arg_rrri *a, gen_helper_gvec_3 *fn)
{
if (sve_access_check(s)) {
TCGContext *tcg_ctx = s->uc->tcg_ctx;
unsigned vsz = vec_full_reg_size(s);
tcg_gen_gvec_3_ool(tcg_ctx, vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
vec_full_reg_offset(s, a->rm),
vsz, vsz, a->imm, fn);
}
return true;
}
static bool trans_ADR_p32(DisasContext *s, arg_rrri *a, uint32_t insn)
{
return do_adr(s, a, gen_helper_sve_adr_p32);
}
static bool trans_ADR_p64(DisasContext *s, arg_rrri *a, uint32_t insn)
{
return do_adr(s, a, gen_helper_sve_adr_p64);
}
static bool trans_ADR_s32(DisasContext *s, arg_rrri *a, uint32_t insn)
{
return do_adr(s, a, gen_helper_sve_adr_s32);
}
static bool trans_ADR_u32(DisasContext *s, arg_rrri *a, uint32_t insn)
{
return do_adr(s, a, gen_helper_sve_adr_u32);
}
/*
*** SVE Predicate Logical Operations Group
*/