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target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV

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The R5900 is taken to be MIPS III with certain modifications. From
MIPS IV it implements the instructions MOVN, MOVZ and PREF.

Backports commit 5601e6217d90ed322b4b9a6d68e8db607db91842 from qemu
This commit is contained in:
Fredrik Noring 2018-11-10 12:08:12 -05:00 committed by Lioncash
parent 296d8bd729
commit cb7b097204
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 3 additions and 2 deletions
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5
qemu/target/mips/translate.c
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@ -23704,7 +23704,7 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
case OPC_MOVN: /* Conditional move */
case OPC_MOVZ:
check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 |
INSN_LOONGSON2E | INSN_LOONGSON2F);
INSN_LOONGSON2E | INSN_LOONGSON2F | INSN_R5900);
gen_cond_move(ctx, op1, rd, rs, rt);
break;
case OPC_MFHI: /* Move from HI/LO */
@ -26570,7 +26570,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat
break;
case OPC_PREF:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 |
INSN_R5900);
/* Treat as NOP. */
break;