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target-arm: make PAR banked

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When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
PAR has a secure and a non-secure instance.

Backports commit 01c097f7960b330c4bf038d34bae17ad6c1ba499 from qemu
This commit is contained in:
Fabian Aggeler 2018-02-12 09:37:39 -05:00 committed by Lioncash
parent ff1ca0608d
commit ccccef3d41
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
16 changed files with 33 additions and 36 deletions
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3
qemu/aarch64.h
View file

@ -2186,7 +2186,6 @@
#define page_flush_tb_1 page_flush_tb_1_aarch64
#define page_init page_init_aarch64
#define page_size_init page_size_init_aarch64
#define par par_aarch64
#define parse_array parse_array_aarch64
#define parse_error parse_error_aarch64
#define parse_escape parse_escape_aarch64
@ -2642,6 +2641,7 @@
#define system_bus_info system_bus_info_aarch64
#define t2ee_cp_reginfo t2ee_cp_reginfo_aarch64
#define table_logic_cc table_logic_cc_aarch64
#define target_el_table target_el_table_aarch64
#define target_parse_constraint target_parse_constraint_aarch64
#define target_words_bigendian target_words_bigendian_aarch64
#define tb_add_jump tb_add_jump_aarch64
@ -3083,7 +3083,6 @@
#define xpsr_write xpsr_write_aarch64
#define xscale_cpar_write xscale_cpar_write_aarch64
#define xscale_cp_reginfo xscale_cp_reginfo_aarch64
#define target_el_table target_el_table_aarch64
#define ARM64_REGS_STORAGE_SIZE ARM64_REGS_STORAGE_SIZE_aarch64
#define arm64_release arm64_release_aarch64
#define arm64_reg_reset arm64_reg_reset_aarch64

3
qemu/aarch64eb.h
View file

@ -2186,7 +2186,6 @@
#define page_flush_tb_1 page_flush_tb_1_aarch64eb
#define page_init page_init_aarch64eb
#define page_size_init page_size_init_aarch64eb
#define par par_aarch64eb
#define parse_array parse_array_aarch64eb
#define parse_error parse_error_aarch64eb
#define parse_escape parse_escape_aarch64eb
@ -2642,6 +2641,7 @@
#define system_bus_info system_bus_info_aarch64eb
#define t2ee_cp_reginfo t2ee_cp_reginfo_aarch64eb
#define table_logic_cc table_logic_cc_aarch64eb
#define target_el_table target_el_table_aarch64eb
#define target_parse_constraint target_parse_constraint_aarch64eb
#define target_words_bigendian target_words_bigendian_aarch64eb
#define tb_add_jump tb_add_jump_aarch64eb
@ -3083,7 +3083,6 @@
#define xpsr_write xpsr_write_aarch64eb
#define xscale_cpar_write xscale_cpar_write_aarch64eb
#define xscale_cp_reginfo xscale_cp_reginfo_aarch64eb
#define target_el_table target_el_table_aarch64eb
#define ARM64_REGS_STORAGE_SIZE ARM64_REGS_STORAGE_SIZE_aarch64eb
#define arm64_release arm64_release_aarch64eb
#define arm64_reg_reset arm64_reg_reset_aarch64eb

3
qemu/arm.h
View file

@ -2186,7 +2186,6 @@
#define page_flush_tb_1 page_flush_tb_1_arm
#define page_init page_init_arm
#define page_size_init page_size_init_arm
#define par par_arm
#define parse_array parse_array_arm
#define parse_error parse_error_arm
#define parse_escape parse_escape_arm
@ -2642,6 +2641,7 @@
#define system_bus_info system_bus_info_arm
#define t2ee_cp_reginfo t2ee_cp_reginfo_arm
#define table_logic_cc table_logic_cc_arm
#define target_el_table target_el_table_arm
#define target_parse_constraint target_parse_constraint_arm
#define target_words_bigendian target_words_bigendian_arm
#define tb_add_jump tb_add_jump_arm
@ -3083,6 +3083,5 @@
#define xpsr_write xpsr_write_arm
#define xscale_cpar_write xscale_cpar_write_arm
#define xscale_cp_reginfo xscale_cp_reginfo_arm
#define target_el_table target_el_table_arm
#define ARM_REGS_STORAGE_SIZE ARM_REGS_STORAGE_SIZE_arm
#endif

3
qemu/armeb.h
View file

@ -2186,7 +2186,6 @@
#define page_flush_tb_1 page_flush_tb_1_armeb
#define page_init page_init_armeb
#define page_size_init page_size_init_armeb
#define par par_armeb
#define parse_array parse_array_armeb
#define parse_error parse_error_armeb
#define parse_escape parse_escape_armeb
@ -2642,6 +2641,7 @@
#define system_bus_info system_bus_info_armeb
#define t2ee_cp_reginfo t2ee_cp_reginfo_armeb
#define table_logic_cc table_logic_cc_armeb
#define target_el_table target_el_table_armeb
#define target_parse_constraint target_parse_constraint_armeb
#define target_words_bigendian target_words_bigendian_armeb
#define tb_add_jump tb_add_jump_armeb
@ -3083,6 +3083,5 @@
#define xpsr_write xpsr_write_armeb
#define xscale_cpar_write xscale_cpar_write_armeb
#define xscale_cp_reginfo xscale_cp_reginfo_armeb
#define target_el_table target_el_table_armeb
#define ARM_REGS_STORAGE_SIZE ARM_REGS_STORAGE_SIZE_armeb
#endif

1
qemu/header_gen.py
View file

@ -2192,7 +2192,6 @@ symbols = (
'page_flush_tb_1',
'page_init',
'page_size_init',
'par',
'parse_array',
'parse_error',
'parse_escape',

3
qemu/m68k.h
View file

@ -2186,7 +2186,6 @@
#define page_flush_tb_1 page_flush_tb_1_m68k
#define page_init page_init_m68k
#define page_size_init page_size_init_m68k
#define par par_m68k
#define parse_array parse_array_m68k
#define parse_error parse_error_m68k
#define parse_escape parse_escape_m68k
@ -2642,6 +2641,7 @@
#define system_bus_info system_bus_info_m68k
#define t2ee_cp_reginfo t2ee_cp_reginfo_m68k
#define table_logic_cc table_logic_cc_m68k
#define target_el_table target_el_table_m68k
#define target_parse_constraint target_parse_constraint_m68k
#define target_words_bigendian target_words_bigendian_m68k
#define tb_add_jump tb_add_jump_m68k
@ -3083,5 +3083,4 @@
#define xpsr_write xpsr_write_m68k
#define xscale_cpar_write xscale_cpar_write_m68k
#define xscale_cp_reginfo xscale_cp_reginfo_m68k
#define target_el_table target_el_table_m68k
#endif

3
qemu/mips.h
View file

@ -2186,7 +2186,6 @@
#define page_flush_tb_1 page_flush_tb_1_mips
#define page_init page_init_mips
#define page_size_init page_size_init_mips
#define par par_mips
#define parse_array parse_array_mips
#define parse_error parse_error_mips
#define parse_escape parse_escape_mips
@ -2642,6 +2641,7 @@
#define system_bus_info system_bus_info_mips
#define t2ee_cp_reginfo t2ee_cp_reginfo_mips
#define table_logic_cc table_logic_cc_mips
#define target_el_table target_el_table_mips
#define target_parse_constraint target_parse_constraint_mips
#define target_words_bigendian target_words_bigendian_mips
#define tb_add_jump tb_add_jump_mips
@ -3083,7 +3083,6 @@
#define xpsr_write xpsr_write_mips
#define xscale_cpar_write xscale_cpar_write_mips
#define xscale_cp_reginfo xscale_cp_reginfo_mips
#define target_el_table target_el_table_mips
#define cpu_mips_exec cpu_mips_exec_mips
#define cpu_mips_get_random cpu_mips_get_random_mips
#define cpu_mips_get_count cpu_mips_get_count_mips

3
qemu/mips64.h
View file

@ -2186,7 +2186,6 @@
#define page_flush_tb_1 page_flush_tb_1_mips64
#define page_init page_init_mips64
#define page_size_init page_size_init_mips64
#define par par_mips64
#define parse_array parse_array_mips64
#define parse_error parse_error_mips64
#define parse_escape parse_escape_mips64
@ -2642,6 +2641,7 @@
#define system_bus_info system_bus_info_mips64
#define t2ee_cp_reginfo t2ee_cp_reginfo_mips64
#define table_logic_cc table_logic_cc_mips64
#define target_el_table target_el_table_mips64
#define target_parse_constraint target_parse_constraint_mips64
#define target_words_bigendian target_words_bigendian_mips64
#define tb_add_jump tb_add_jump_mips64
@ -3083,7 +3083,6 @@
#define xpsr_write xpsr_write_mips64
#define xscale_cpar_write xscale_cpar_write_mips64
#define xscale_cp_reginfo xscale_cp_reginfo_mips64
#define target_el_table target_el_table_mips64
#define cpu_mips_exec cpu_mips_exec_mips64
#define cpu_mips_get_random cpu_mips_get_random_mips64
#define cpu_mips_get_count cpu_mips_get_count_mips64

3
qemu/mips64el.h
View file

@ -2186,7 +2186,6 @@
#define page_flush_tb_1 page_flush_tb_1_mips64el
#define page_init page_init_mips64el
#define page_size_init page_size_init_mips64el
#define par par_mips64el
#define parse_array parse_array_mips64el
#define parse_error parse_error_mips64el
#define parse_escape parse_escape_mips64el
@ -2642,6 +2641,7 @@
#define system_bus_info system_bus_info_mips64el
#define t2ee_cp_reginfo t2ee_cp_reginfo_mips64el
#define table_logic_cc table_logic_cc_mips64el
#define target_el_table target_el_table_mips64el
#define target_parse_constraint target_parse_constraint_mips64el
#define target_words_bigendian target_words_bigendian_mips64el
#define tb_add_jump tb_add_jump_mips64el
@ -3083,7 +3083,6 @@
#define xpsr_write xpsr_write_mips64el
#define xscale_cpar_write xscale_cpar_write_mips64el
#define xscale_cp_reginfo xscale_cp_reginfo_mips64el
#define target_el_table target_el_table_mips64el
#define cpu_mips_exec cpu_mips_exec_mips64el
#define cpu_mips_get_random cpu_mips_get_random_mips64el
#define cpu_mips_get_count cpu_mips_get_count_mips64el

3
qemu/mipsel.h
View file

@ -2186,7 +2186,6 @@
#define page_flush_tb_1 page_flush_tb_1_mipsel
#define page_init page_init_mipsel
#define page_size_init page_size_init_mipsel
#define par par_mipsel
#define parse_array parse_array_mipsel
#define parse_error parse_error_mipsel
#define parse_escape parse_escape_mipsel
@ -2642,6 +2641,7 @@
#define system_bus_info system_bus_info_mipsel
#define t2ee_cp_reginfo t2ee_cp_reginfo_mipsel
#define table_logic_cc table_logic_cc_mipsel
#define target_el_table target_el_table_mipsel
#define target_parse_constraint target_parse_constraint_mipsel
#define target_words_bigendian target_words_bigendian_mipsel
#define tb_add_jump tb_add_jump_mipsel
@ -3083,7 +3083,6 @@
#define xpsr_write xpsr_write_mipsel
#define xscale_cpar_write xscale_cpar_write_mipsel
#define xscale_cp_reginfo xscale_cp_reginfo_mipsel
#define target_el_table target_el_table_mipsel
#define cpu_mips_exec cpu_mips_exec_mipsel
#define cpu_mips_get_random cpu_mips_get_random_mipsel
#define cpu_mips_get_count cpu_mips_get_count_mipsel

3
qemu/powerpc.h
View file

@ -2186,7 +2186,6 @@
#define page_flush_tb_1 page_flush_tb_1_powerpc
#define page_init page_init_powerpc
#define page_size_init page_size_init_powerpc
#define par par_powerpc
#define parse_array parse_array_powerpc
#define parse_error parse_error_powerpc
#define parse_escape parse_escape_powerpc
@ -2642,6 +2641,7 @@
#define system_bus_info system_bus_info_powerpc
#define t2ee_cp_reginfo t2ee_cp_reginfo_powerpc
#define table_logic_cc table_logic_cc_powerpc
#define target_el_table target_el_table_powerpc
#define target_parse_constraint target_parse_constraint_powerpc
#define target_words_bigendian target_words_bigendian_powerpc
#define tb_add_jump tb_add_jump_powerpc
@ -3083,5 +3083,4 @@
#define xpsr_write xpsr_write_powerpc
#define xscale_cpar_write xscale_cpar_write_powerpc
#define xscale_cp_reginfo xscale_cp_reginfo_powerpc
#define target_el_table target_el_table_powerpc
#endif

3
qemu/sparc.h
View file

@ -2186,7 +2186,6 @@
#define page_flush_tb_1 page_flush_tb_1_sparc
#define page_init page_init_sparc
#define page_size_init page_size_init_sparc
#define par par_sparc
#define parse_array parse_array_sparc
#define parse_error parse_error_sparc
#define parse_escape parse_escape_sparc
@ -2642,6 +2641,7 @@
#define system_bus_info system_bus_info_sparc
#define t2ee_cp_reginfo t2ee_cp_reginfo_sparc
#define table_logic_cc table_logic_cc_sparc
#define target_el_table target_el_table_sparc
#define target_parse_constraint target_parse_constraint_sparc
#define target_words_bigendian target_words_bigendian_sparc
#define tb_add_jump tb_add_jump_sparc
@ -3083,7 +3083,6 @@
#define xpsr_write xpsr_write_sparc
#define xscale_cpar_write xscale_cpar_write_sparc
#define xscale_cp_reginfo xscale_cp_reginfo_sparc
#define target_el_table target_el_table_sparc
#define cpu_sparc_exec cpu_sparc_exec_sparc
#define helper_compute_psr helper_compute_psr_sparc
#define helper_compute_C_icc helper_compute_C_icc_sparc

3
qemu/sparc64.h
View file

@ -2186,7 +2186,6 @@
#define page_flush_tb_1 page_flush_tb_1_sparc64
#define page_init page_init_sparc64
#define page_size_init page_size_init_sparc64
#define par par_sparc64
#define parse_array parse_array_sparc64
#define parse_error parse_error_sparc64
#define parse_escape parse_escape_sparc64
@ -2642,6 +2641,7 @@
#define system_bus_info system_bus_info_sparc64
#define t2ee_cp_reginfo t2ee_cp_reginfo_sparc64
#define table_logic_cc table_logic_cc_sparc64
#define target_el_table target_el_table_sparc64
#define target_parse_constraint target_parse_constraint_sparc64
#define target_words_bigendian target_words_bigendian_sparc64
#define tb_add_jump tb_add_jump_sparc64
@ -3083,7 +3083,6 @@
#define xpsr_write xpsr_write_sparc64
#define xscale_cpar_write xscale_cpar_write_sparc64
#define xscale_cp_reginfo xscale_cp_reginfo_sparc64
#define target_el_table target_el_table_sparc64
#define cpu_sparc_exec cpu_sparc_exec_sparc64
#define helper_compute_psr helper_compute_psr_sparc64
#define helper_compute_C_icc helper_compute_C_icc_sparc64

10
qemu/target-arm/cpu.h
View file

@ -281,7 +281,15 @@ typedef struct CPUARMState {
};
uint64_t far_el[4];
};
uint64_t par_el1; /* Translation result. */
union { /* Translation result. */
struct {
uint64_t _unused_par_0;
uint64_t par_ns;
uint64_t _unused_par_1;
uint64_t par_s;
};
uint64_t par_el[4];
};
uint32_t c9_insn; /* Cache lockdown registers. */
uint32_t c9_data;
uint64_t c9_pmcr; /* performance monitor control register */

19
qemu/target-arm/helper.c
View file

@ -1181,6 +1181,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
int prot;
int ret, is_user = ri->opc2 & 2;
int access_type = ri->opc2 & 1;
uint64_t par64;
ret = get_phys_addr(env, value, access_type, is_user,
&phys_addr, &prot, &page_size);
@ -1189,7 +1190,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
* translation table format, but with WnR always clear.
* Convert it to a 64-bit PAR.
*/
uint64_t par64 = (1 << 11); /* LPAE bit always set */
par64 = (1 << 11); /* LPAE bit always set */
if (ret == 0) {
par64 |= phys_addr & ~0xfffULL;
/* We don't set the ATTR or SH fields in the PAR. */
@ -1201,7 +1202,6 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
* fault.
*/
}
env->cp15.par_el1 = par64;
} else {
/* ret is a DFSR/IFSR value for the short descriptor
* translation table format (with WnR always clear).
@ -1211,22 +1211,24 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
/* We do not set any attribute bits in the PAR */
if (page_size == (1 << 24)
&& arm_feature(env, ARM_FEATURE_V7)) {
env->cp15.par_el1 = (phys_addr & 0xff000000) | 1 << 1;
par64 = (phys_addr & 0xff000000) | 1 << 1;
} else {
env->cp15.par_el1 = phys_addr & 0xfffff000;
par64 = phys_addr & 0xfffff000;
}
} else {
env->cp15.par_el1 = ((ret & (1 << 10)) >> 5) |
((ret & (1 << 12)) >> 6) |
par64 = ((ret & (1 << 10)) >> 5) | ((ret & (1 << 12)) >> 6) |
((ret & 0xf) << 1) | 1;
}
}
A32_BANKED_CURRENT_REG_SET(env, par, par64);
}
#endif
static const ARMCPRegInfo vapa_cp_reginfo[] = {
{ "PAR", 15,7,4, 0,0,0, 0,
0, PL1_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.par_el1), {0, 0},
0, PL1_RW, 0, NULL, 0, 0,
{ offsetoflow32(CPUARMState, cp15.par_s), offsetoflow32(CPUARMState, cp15.par_ns) },
NULL, NULL, par_write },
#ifndef CONFIG_USER_ONLY
{ "ATS", 15,7,8, 0,0,CP_ANY, 0,
@ -1621,7 +1623,8 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
{ "AMAIR1", 15,10,3, 0,0,1, 0,
ARM_CP_CONST | ARM_CP_OVERRIDE, PL1_RW, 0, NULL, 0 },
{ "PAR", 15, 0,7, 0,0, 0, 0,
ARM_CP_64BIT, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.par_el1), },
ARM_CP_64BIT, PL1_RW, 0, NULL, 0, 0,
{ offsetof(CPUARMState, cp15.par_s), offsetof(CPUARMState, cp15.par_ns) } },
{ "TTBR0", 15, 0,2, 0,0, 0, 0,
ARM_CP_64BIT | ARM_CP_NO_MIGRATE, PL1_RW, 0, NULL, 0, 0,
{ offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) },

3
qemu/x86_64.h
View file

@ -2186,7 +2186,6 @@
#define page_flush_tb_1 page_flush_tb_1_x86_64
#define page_init page_init_x86_64
#define page_size_init page_size_init_x86_64
#define par par_x86_64
#define parse_array parse_array_x86_64
#define parse_error parse_error_x86_64
#define parse_escape parse_escape_x86_64
@ -2642,6 +2641,7 @@
#define system_bus_info system_bus_info_x86_64
#define t2ee_cp_reginfo t2ee_cp_reginfo_x86_64
#define table_logic_cc table_logic_cc_x86_64
#define target_el_table target_el_table_x86_64
#define target_parse_constraint target_parse_constraint_x86_64
#define target_words_bigendian target_words_bigendian_x86_64
#define tb_add_jump tb_add_jump_x86_64
@ -3083,5 +3083,4 @@
#define xpsr_write xpsr_write_x86_64
#define xscale_cpar_write xscale_cpar_write_x86_64
#define xscale_cp_reginfo xscale_cp_reginfo_x86_64
#define target_el_table target_el_table_x86_64
#endif