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target/riscv: Fix pmp NA4 implementation

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The end address calculation for NA4 mode is wrong because the address
used isn't shifted.

It doesn't watch 4 bytes but a huge range because the end address
calculation is wrong.

The solution is to use the shifted address calculated for start address
variable.

Modifications are tested on Zephyr OS userspace test suite which works
for other RISC-V boards (E31 and E34 core).

Backports cfad709bceb629a4ebeb5d8a3acd1871b9a6436b
This commit is contained in:
Alexandre Mergnat 2021-03-08 12:14:42 -05:00 committed by Lioncash
parent b1e52b7958
commit cd956f5aa6
1 changed files with 1 additions and 1 deletions
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2
qemu/target/riscv/pmp.c
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@ -181,7 +181,7 @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index)
case PMP_AMATCH_NA4:
sa = this_addr << 2; /* shift up from [xx:0] to [xx+2:2] */
ea = (this_addr + 4u) - 1u;
ea = (sa + 4u) - 1u;
break;
case PMP_AMATCH_NAPOT: