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target/riscv: check before allocating TCG temps

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Backports ec80f8745931f0c8f8f2251e16bcc69170cf6f27
This commit is contained in:
LIU Zhiwei 2021-03-08 12:41:17 -05:00 committed by Lioncash
parent 8fe29be764
commit cde007ccb6
2 changed files with 8 additions and 8 deletions
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8
qemu/target/riscv/insn_trans/trans_rvd.inc.c
View file

@ -22,10 +22,10 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
{ {
TCGContext *tcg_ctx = ctx->uc->tcg_ctx; TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(ctx, t0, a->rs1);
REQUIRE_FPU; REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD); REQUIRE_EXT(ctx, RVD);
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(ctx, t0, a->rs1);
tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm); tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm);
tcg_gen_qemu_ld_i64(ctx->uc, tcg_ctx->cpu_fpr_risc[a->rd], t0, ctx->mem_idx, MO_TEQ); tcg_gen_qemu_ld_i64(ctx->uc, tcg_ctx->cpu_fpr_risc[a->rd], t0, ctx->mem_idx, MO_TEQ);
@ -39,10 +39,10 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
{ {
TCGContext *tcg_ctx = ctx->uc->tcg_ctx; TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(ctx, t0, a->rs1);
REQUIRE_FPU; REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD); REQUIRE_EXT(ctx, RVD);
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(ctx, t0, a->rs1);
tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm); tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm);
tcg_gen_qemu_st_i64(ctx->uc, tcg_ctx->cpu_fpr_risc[a->rs2], t0, ctx->mem_idx, MO_TEQ); tcg_gen_qemu_st_i64(ctx->uc, tcg_ctx->cpu_fpr_risc[a->rs2], t0, ctx->mem_idx, MO_TEQ);

8
qemu/target/riscv/insn_trans/trans_rvf.inc.c
View file

@ -26,10 +26,10 @@
static bool trans_flw(DisasContext *ctx, arg_flw *a) static bool trans_flw(DisasContext *ctx, arg_flw *a)
{ {
TCGContext *tcg_ctx = ctx->uc->tcg_ctx; TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(ctx, t0, a->rs1);
REQUIRE_FPU; REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF); REQUIRE_EXT(ctx, RVF);
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(ctx, t0, a->rs1);
tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm); tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm);
tcg_gen_qemu_ld_i64(ctx->uc, tcg_ctx->cpu_fpr_risc[a->rd], t0, ctx->mem_idx, MO_TEUL); tcg_gen_qemu_ld_i64(ctx->uc, tcg_ctx->cpu_fpr_risc[a->rd], t0, ctx->mem_idx, MO_TEUL);
@ -43,11 +43,11 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
static bool trans_fsw(DisasContext *ctx, arg_fsw *a) static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
{ {
TCGContext *tcg_ctx = ctx->uc->tcg_ctx; TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
TCGv t0 = tcg_temp_new(tcg_ctx); TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(ctx, t0, a->rs1); gen_get_gpr(ctx, t0, a->rs1);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm); tcg_gen_addi_tl(tcg_ctx, t0, t0, a->imm);
tcg_gen_qemu_st_i64(ctx->uc, tcg_ctx->cpu_fpr_risc[a->rs2], t0, ctx->mem_idx, MO_TEUL); tcg_gen_qemu_st_i64(ctx->uc, tcg_ctx->cpu_fpr_risc[a->rs2], t0, ctx->mem_idx, MO_TEUL);