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target-arm: Use new deposit and extract ops

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Use the new primitives for UBFX and SBFX.

Backports commits 59a71b4c5b4ef2ef6425b9e21c972dd5bf450275 and 86c9ab277615af4e0389eb80a83073873ff96c86 from qemu
This commit is contained in:
Richard Henderson 2018-03-01 13:49:53 -05:00 committed by Lioncash
parent f0781470b4
commit ce3c153bd8
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 38 additions and 85 deletions
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84
qemu/target-arm/translate-a64.c
View file

@ -3278,68 +3278,44 @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
low 32-bits anyway. */
tcg_tmp = read_cpu_reg(s, rn, 1);
/* Recognize the common aliases. */
if (opc == 0) { /* SBFM */
if (ri == 0) {
if (si == 7) { /* SXTB */
tcg_gen_ext8s_i64(tcg_ctx, tcg_rd, tcg_tmp);
goto done;
} else if (si == 15) { /* SXTH */
tcg_gen_ext16s_i64(tcg_ctx, tcg_rd, tcg_tmp);
goto done;
} else if (si == 31) { /* SXTW */
tcg_gen_ext32s_i64(tcg_ctx, tcg_rd, tcg_tmp);
goto done;
}
}
if (si == 63 || (si == 31 && ri <= si)) { /* ASR */
if (si == 31) {
tcg_gen_ext32s_i64(tcg_ctx, tcg_tmp, tcg_tmp);
}
tcg_gen_sari_i64(tcg_ctx, tcg_rd, tcg_tmp, ri);
goto done;
}
} else if (opc == 2) { /* UBFM */
if (ri == 0) { /* UXTB, UXTH, plus non-canonical AND */
tcg_gen_andi_i64(tcg_ctx, tcg_rd, tcg_tmp, bitmask64(si + 1));
return;
}
if (si == 63 || (si == 31 && ri <= si)) { /* LSR */
if (si == 31) {
tcg_gen_ext32u_i64(tcg_ctx, tcg_tmp, tcg_tmp);
}
tcg_gen_shri_i64(tcg_ctx, tcg_rd, tcg_tmp, ri);
return;
}
if (si + 1 == ri && si != bitsize - 1) { /* LSL */
int shift = bitsize - 1 - si;
tcg_gen_shli_i64(tcg_ctx, tcg_rd, tcg_tmp, shift);
goto done;
}
}
if (opc != 1) { /* SBFM or UBFM */
tcg_gen_movi_i64(tcg_ctx, tcg_rd, 0);
}
/* do the bit move operation */
/* Recognize simple(r) extractions. */
if (si >= ri) {
/* Wd<s-r:0> = Wn<s:r> */
tcg_gen_shri_i64(tcg_ctx, tcg_tmp, tcg_tmp, ri);
pos = 0;
len = (si - ri) + 1;
if (opc == 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
tcg_gen_sextract_i64(tcg_ctx, tcg_rd, tcg_tmp, ri, len);
goto done;
} else if (opc == 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
tcg_gen_extract_i64(tcg_ctx, tcg_rd, tcg_tmp, ri, len);
return;
}
/* opc == 1, BXFIL fall through to deposit */
tcg_gen_extract_i64(tcg_ctx, tcg_tmp, tcg_tmp, ri, len);
pos = 0;
} else {
/* Wd<32+s-r,32-r> = Wn<s:0> */
pos = bitsize - ri;
/* Handle the ri > si case with a deposit
* Wd<32+s-r,32-r> = Wn<s:0>
*/
len = si + 1;
pos = (bitsize - ri) & (bitsize - 1);
}
tcg_gen_deposit_i64(tcg_ctx, tcg_rd, tcg_rd, tcg_tmp, pos, len);
if (opc == 0 && len < ri) {
/* SBFM: sign extend the destination field from len to fill
the balance of the word. Let the deposit below insert all
of those sign bits. */
tcg_gen_sextract_i64(tcg_ctx, tcg_tmp, tcg_tmp, 0, len);
len = ri;
}
if (opc == 0) { /* SBFM - sign extend the destination field */
tcg_gen_shli_i64(tcg_ctx, tcg_rd, tcg_rd, 64 - (pos + len));
tcg_gen_sari_i64(tcg_ctx, tcg_rd, tcg_rd, 64 - (pos + len));
if (opc == 1) { /* BFM, BXFIL */
tcg_gen_deposit_i64(tcg_ctx, tcg_rd, tcg_rd, tcg_tmp, pos, len);
} else {
/* SBFM or UBFM: We start with zero, and we haven't modified
any bits outside bitsize, therefore the zero-extension
below is unneeded. */
tcg_gen_deposit_z_i64(tcg_ctx, tcg_rd, tcg_tmp, pos, len);
return;
}
done:

39
qemu/target-arm/translate.c
View file

@ -287,31 +287,6 @@ static void gen_revsh(DisasContext *s, TCGv_i32 var)
tcg_gen_ext16s_i32(tcg_ctx, var, var);
}
/* Unsigned bitfield extract. */
static void gen_ubfx(DisasContext *s, TCGv_i32 var, int shift, uint32_t mask)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
if (shift)
tcg_gen_shri_i32(tcg_ctx, var, var, shift);
tcg_gen_andi_i32(tcg_ctx, var, var, mask);
}
/* Signed bitfield extract. */
static void gen_sbfx(DisasContext *s, TCGv_i32 var, int shift, int width)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
uint32_t signbit;
if (shift)
tcg_gen_sari_i32(tcg_ctx, var, var, shift);
if (shift + width < 32) {
signbit = 1u << (width - 1);
tcg_gen_andi_i32(tcg_ctx, var, var, (1u << width) - 1);
tcg_gen_xori_i32(tcg_ctx, var, var, signbit);
tcg_gen_subi_i32(tcg_ctx, var, var, signbit);
}
}
/* Return (b << 32) + a. Mark inputs as dead */
static TCGv_i64 gen_addq_msw(DisasContext *s, TCGv_i64 a, TCGv_i32 b)
{
@ -9333,9 +9308,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) // qq
goto illegal_op;
if (i < 32) {
if (op1 & 0x20) {
gen_ubfx(s, tmp, shift, (1u << i) - 1);
tcg_gen_extract_i32(tcg_ctx, tmp, tmp, shift, i);
} else {
gen_sbfx(s, tmp, shift, i);
tcg_gen_sextract_i32(tcg_ctx, tmp, tmp, shift, i);
}
}
store_reg(s, rd, tmp);
@ -10654,15 +10629,17 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
imm++;
if (shift + imm > 32)
goto illegal_op;
if (imm < 32)
gen_sbfx(s, tmp, shift, imm);
if (imm < 32) {
tcg_gen_sextract_i32(tcg_ctx, tmp, tmp, shift, imm);
}
break;
case 6: /* Unsigned bitfield extract. */
imm++;
if (shift + imm > 32)
goto illegal_op;
if (imm < 32)
gen_ubfx(s, tmp, shift, (1u << imm) - 1);
if (imm < 32) {
tcg_gen_extract_i32(tcg_ctx, tmp, tmp, shift, imm);
}
break;
case 3: /* Bitfield insert/clear. */
if (imm < shift)