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target/arm: Fix aarch64_sve_change_el wrt EL0

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At present we assert:

arm_el_is_aa64: Assertion `el >= 1 && el <= 3' failed.

The comment in arm_el_is_aa64 explains why asking about EL0 without
extra information is impossible. Add an extra argument to provide
it from the surrounding context.

Fixes: 0ab5953b00b3

Backports commit 9a05f7b67436abdc52bce899f56acfde2e831454 from qemu
This commit is contained in:
Richard Henderson 2018-10-23 12:43:51 -04:00 committed by Lioncash
parent ff812cc152
commit ce9485a63e
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 22 additions and 7 deletions
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7
qemu/target/arm/cpu.h
View file

@ -855,10 +855,13 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
#ifdef TARGET_AARCH64
void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el);
void aarch64_sve_change_el(CPUARMState *env, int old_el,
int new_el, bool el0_a64);
#else
static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
static inline void aarch64_sve_change_el(CPUARMState *env, int o, int n) { }
static inline void aarch64_sve_change_el(CPUARMState *env, int o,
int n, bool a)
{ }
#endif
target_ulong do_arm_semihosting(CPUARMState *env);

16
qemu/target/arm/helper.c
View file

@ -7572,7 +7572,11 @@ static void arm_cpu_do_interrupt_aarch64_(CPUState *cs)
unsigned int new_mode = aarch64_pstate_mode(new_el, true);
unsigned int cur_el = arm_current_el(env);
aarch64_sve_change_el(env, cur_el, new_el);
/*
* Note that new_el can never be 0. If cur_el is 0, then
* el0_a64 is is_a64(), else el0_a64 is ignored.
*/
aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
if (cur_el < new_el) {
/* Entry vector offset depends on whether the implemented EL
@ -12021,9 +12025,11 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
/*
* Notice a change in SVE vector size when changing EL.
*/
void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el)
void aarch64_sve_change_el(CPUARMState *env, int old_el,
int new_el, bool el0_a64)
{
int old_len, new_len;
bool old_a64, new_a64;
/* Nothing to do if no SVE. */
if (!arm_feature(env, ARM_FEATURE_SVE)) {
@ -12047,9 +12053,11 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el)
* we already have the correct register contents when encountering the
* vq0->vq0 transition between EL0->EL1.
*/
old_len = (arm_el_is_aa64(env, old_el) && !sve_exception_el(env, old_el)
old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64;
old_len = (old_a64 && !sve_exception_el(env, old_el)
? sve_zcr_len_for_el(env, old_el) : 0);
new_len = (arm_el_is_aa64(env, new_el) && !sve_exception_el(env, new_el)
new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64;
new_len = (new_a64 && !sve_exception_el(env, new_el)
? sve_zcr_len_for_el(env, new_el) : 0);
/* When changing vector length, clear inaccessible state. */

6
qemu/target/arm/op_helper.c
View file

@ -1079,7 +1079,11 @@ void HELPER(exception_return)(CPUARMState *env)
"AArch64 EL%d PC 0x%" PRIx64 "\n",
cur_el, new_el, env->pc);
}
aarch64_sve_change_el(env, cur_el, new_el);
/*
* Note that cur_el can never be 0. If new_el is 0, then
* el0_a64 is return_to_aa64, else el0_a64 is ignored.
*/
aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64);
arm_call_el_change_hook(arm_env_get_cpu(env));