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target/arm: Clear exclusive monitor on v7M reset, exception entry/exit

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For M profile we must clear the exclusive monitor on reset, exception
entry and exception exit. We weren't doing any of these things; fix
this bug.

Backports commit dc3c4c14f0f12854dbd967be3486f4db4e66d25b from qemu
This commit is contained in:
Peter Maydell 2018-03-04 23:09:38 -05:00 committed by Lioncash
parent 2a9b62c12b
commit ceccd92940
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GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 13 additions and 1 deletions
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2
qemu/target/arm/helper.c
View file

@ -5434,6 +5434,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr)
// Unicorn: commented out
//armv7m_nvic_acknowledge_irq(env->nvic);
switch_v7m_sp(env, 0);
arm_clear_exclusive(env);
/* Clear IT bits */
env->condexec_bits = 0;
env->regs[14] = lr;
@ -5620,6 +5621,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
}
/* Otherwise, we have a successful exception exit. */
arm_clear_exclusive(env);
qemu_log_mask(CPU_LOG_INT, "...successful exception return\n");
}

10
qemu/target/arm/internals.h
View file

@ -445,6 +445,16 @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
void arm_handle_psci_call(ARMCPU *cpu);
#endif
/**
* arm_clear_exclusive: clear the exclusive monitor
* @env: CPU env
* Clear the CPU's exclusive monitor, like the guest CLREX instruction.
*/
static inline void arm_clear_exclusive(CPUARMState *env)
{
env->exclusive_addr = -1;
}
/**
* ARMMMUFaultInfo: Information describing an ARM MMU Fault
* @s2addr: Address that caused a fault at stage 2

2
qemu/target/arm/op_helper.c
View file

@ -997,7 +997,7 @@ void HELPER(exception_return)(CPUARMState *env)
aarch64_save_sp(env, cur_el);
env->exclusive_addr = -1;
arm_clear_exclusive(env);
/* We must squash the PSTATE.SS bit to zero unless both of the
* following hold: