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target/arm: Clear exclusive monitor on v7M reset, exception entry/exit
For M profile we must clear the exclusive monitor on reset, exception entry and exception exit. We weren't doing any of these things; fix this bug. Backports commit dc3c4c14f0f12854dbd967be3486f4db4e66d25b from qemu
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2a9b62c12b
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ceccd92940
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@ -5434,6 +5434,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr)
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// Unicorn: commented out
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//armv7m_nvic_acknowledge_irq(env->nvic);
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switch_v7m_sp(env, 0);
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arm_clear_exclusive(env);
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/* Clear IT bits */
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env->condexec_bits = 0;
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env->regs[14] = lr;
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@ -5620,6 +5621,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)
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}
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/* Otherwise, we have a successful exception exit. */
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arm_clear_exclusive(env);
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qemu_log_mask(CPU_LOG_INT, "...successful exception return\n");
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}
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@ -445,6 +445,16 @@ bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
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void arm_handle_psci_call(ARMCPU *cpu);
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#endif
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/**
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* arm_clear_exclusive: clear the exclusive monitor
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* @env: CPU env
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* Clear the CPU's exclusive monitor, like the guest CLREX instruction.
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*/
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static inline void arm_clear_exclusive(CPUARMState *env)
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{
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env->exclusive_addr = -1;
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}
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/**
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* ARMMMUFaultInfo: Information describing an ARM MMU Fault
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* @s2addr: Address that caused a fault at stage 2
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@ -997,7 +997,7 @@ void HELPER(exception_return)(CPUARMState *env)
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aarch64_save_sp(env, cur_el);
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env->exclusive_addr = -1;
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arm_clear_exclusive(env);
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/* We must squash the PSTATE.SS bit to zero unless both of the
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* following hold:
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